公开(公告)号：US20160164529A1

公开(公告)日：2016-06-09

申请号：US15043137

申请日：2016-02-12

Applicant: Renesas Electronics Corporation

Inventor： Takashi Nakamura ,  Kosuke YAYAMA ,  Masaaki IIJIMA

IPC: H03L7/099

CPC classification number: H03L7/0991 ,  H03L1/022 ,  H03L7/00 ,  H03L7/02 ,  H03L7/06 ,  H03L7/099 ,  H03L7/16 ,  H03L7/22 ,  H03L2207/06 ,  H03L2207/50

Abstract: A frequency-locked loop circuit includes a digital control oscillator that generates a clock, and an FLL (frequency-locked loop) controller that generates a frequency control code to control an oscillation frequency of the clock. The FLL controller includes a frequency comparison unit that compares a frequency of a clock generated by the digital control oscillator with a frequency of a multiplied reference clock, and a delay code control unit that generates, based on a comparison result of the frequency comparison unit, the frequency control code so that the frequency of the clock generated by the digital control oscillator matches the frequency of the multiplied reference clock, the frequency comparison unit determines the frequency of the clock, and the delay code control unit generates the frequency control code according to a determination result of the frequency comparison unit, and outputs the frequency control code to the digital control oscillator.

Abstract translation: 锁频环路电路包括产生时钟的数字控制振荡器和产生用于控制时钟的振荡频率的频率控制码的FLL（锁频环路）控制器。 FLL控制器包括频率比较单元，其将由数字控制振荡器产生的时钟的频率与相乘的参考时钟的频率进行比较;以及延迟码控制单元，其基于频率比较单元的比较结果， 频率控制代码，使得由数字控制振荡器产生的时钟频率与倍增的参考时钟的频率相匹配，频率比较单元确定时钟的频率，并且延迟码控制单元根据 频率比较单元的确定结果，并将频率控制代码输出到数字控制振荡器。