公开(公告)号：US20240428024A1

公开(公告)日：2024-12-26

申请号：US18339504

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Sagar Koorapati ,  Vinod Chamarty ,  Alon Naveh

IPC: G06K7/10

Abstract: Broadcasting power limiting management responses in a processor-based system in an integrated circuit (IC) chip is disclosed herein. In one aspect, an IC chip comprises a processor-based system that includes a power estimation and limiting (PEL) circuit, a Limit Management Throughput Throttle (LMTT) source circuit, a plurality of activity management (AM) circuits, and an LMTT bus communicatively coupling the LMTT source circuit with each AM circuit of the plurality of AM circuits. The LMTT source circuit receives a power limiting management response from a PEL circuit via a communications network of the processor-based system, and generates an LMTT command based on the power limiting management response. The LMTT source circuit broadcasts the LMTT command to each AM circuit of the plurality of AM circuits via the LMTT bus.

公开(公告)号：US20240427682A1

公开(公告)日：2024-12-26

申请号：US18339520

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Sagar Koorapati ,  Pradeep Kanapathipillai ,  Alon Naveh

IPC: G06F11/30 ,  G06F1/3206

Abstract: Converting telemetry values into common data formats in a processor-based system in an integrated circuit (IC) chip is disclosed herein. In one aspect, an IC chip comprises a processor-based system that that is configured to receive an input telemetry value from an input source circuit. The processor-based system converts the input telemetry value into a common format telemetry value, wherein a first unit value represented by a least significant bit of the common format telemetry value is greater than one (1) and is based on a quotient of a power of two (2) and a corresponding power of 10. The processor-based system then processes common format telemetry value.

公开(公告)号：US20240427393A1

公开(公告)日：2024-12-26

申请号：US18626683

申请日：2024-04-04

Applicant: QUALCOMM Incorporated

Inventor： Vinod Chamarty ,  Sagar Koorapati ,  Sreeram Jayadev ,  Alon Naveh

IPC: G06F1/26

Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The circuit levels in the hierarchical power management systems are configured to be time synchronized with each other for the synchronized monitoring and reporting of activity samples and activity power events, and the generation of power limiting management responses to throttle power consumption in the IC chip.

公开(公告)号：US20240427392A1

公开(公告)日：2024-12-26

申请号：US18339430

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Vinod Chamarty ,  Sagar Koorapati ,  Sreeram Jayadev ,  Alon Naveh

IPC: G06F1/26

Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The circuit levels in the hierarchical power management systems are configured to be time synchronized with each other for the synchronized monitoring and reporting of activity samples and activity power events, and the generation of power limiting management responses to throttle power consumption in the IC chip.