公开(公告)号：US12153527B2

公开(公告)日：2024-11-26

申请号：US18081396

申请日：2022-12-14

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy Akavaram ,  Prakhar Srivastava ,  Rajendra Varma Pusapati ,  Ravindranath Doddi ,  Yogananda Rao Chillariga

IPC: G06F13/40 ,  G06F13/12

Abstract: Aspects relate to lane failure recovery for a data link having multiple lanes labeled in a contiguous sequence. In one aspect, a failure of a failed lane of the data link is detected. Working lanes of the data link are then detected. A set of contiguous working lanes of the data link are selected, and an operational link as including the selected set of contiguous working lanes is defined. A start address of the operational link is identified and stored in a configuration register. Data traffic is transmitted on the operational link.

公开(公告)号：US12271303B2

公开(公告)日：2025-04-08

申请号：US18349206

申请日：2023-07-10

Applicant: QUALCOMM Incorporated

Inventor： Manish Garg ,  Pratibind Kumar Jha ,  Prakhar Srivastava ,  Santhosh Reddy Akavaram

IPC: G06F12/02

Abstract: Methods that may be performed by a host controller and a memory controller of a computing device. The method synchronizes memory tables between the storage device and a host device by modifying an indicator in a first memory table on the storage device in response to a change in a memory mapping, the first memory table mapping logical addresses to physical addresses of memory on the storage device, the indicator identifying one or more address mapping changes of the first memory table, notifying the host device that the first memory table has been modified, and transmitting to the host device at least a portion of the first memory table including the one or more address mapping changes. The storage device processes memory requests from the host device based on one or more addresses affected by the one or more address mapping changes.

公开(公告)号：US12056364B1

公开(公告)日：2024-08-06

申请号：US18296319

申请日：2023-04-05

Applicant: QUALCOMM Incorporated

Inventor： Yogananda Rao Chillariga ,  Santhosh Reddy Akavaram ,  Prakhar Srivastava ,  Sonali Jabreva ,  Chintalapati Bharath Sai Varma

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0656 ,  G06F3/0679

Abstract: Aspects of the present disclosure provide various techniques, apparatuses, and methods that can improve the memory resource utilization of a data storage device that uses nonvolatile memory (NVM) to store data. In some aspects, the data storage device can be provided with multiple write buffers to improve the write throughput of the device. In some aspects, the data storage device can use a utilization array to keep track of the utilization information of each write buffer. In some aspects, the data storage device can repurpose the memory of a write buffer with low utilization to serve an active logical unit which becomes full, thus preserving the function of the write buffer of the active logical unit.