公开(公告)号：US20190266098A1

公开(公告)日：2019-08-29

申请号：US15908637

申请日：2018-02-28

Applicant: QUALCOMM Incorporated

Inventor： Andrew Torchalski ,  Edwin Jose ,  Joshua Stubbs

IPC: G06F12/0891 ,  G06F3/06

Abstract: Various embodiments include methods and devices for implementing progressive flush of a cache memory of a computing device. Various embodiments may include determining an activity state of a region of the cache memory, issuing a start cache memory flush command in response to determining that the activity state of the region is idle, flushing the region in response to the start cache memory flush command, determining that the activity state of the region is active, issuing an abort cache memory flush command in response to determining that the activity state of the region is active, and aborting flushing the region in response to the abort cache memory flush command.

公开(公告)号：US10331526B2

公开(公告)日：2019-06-25

申请号：US15170742

申请日：2016-06-01

Applicant: QUALCOMM Incorporated

Inventor： Edwin Jose ,  Tao Wang

IPC: G06F11/14 ,  G06F3/06 ,  G06F13/16

Abstract: Some aspects of the disclosure include a self-refresh entry sequence for a memory, such as a DRAM, that may be used to avoid a frequency mismatch between a system processor and a system memory. The self-refresh entry sequence may signal the memory to reset the frequency set point state and default to the power-up state upon a self-refresh process exit. In another aspect, a new mode register may be used to indicate that the frequency set point needs to be reset after the next self-refresh entry command. In this aspect, the processor will execute a mode register write command followed by a self-refresh entry in response to the occurrence of a crash event. Then, the memory will reset to the default frequency set point by the end of self-refresh entry execution.