公开(公告)号：US20220294433A1

公开(公告)日：2022-09-15

申请号：US17198515

申请日：2021-03-11

Applicant: QUALCOMM INCORPORATED

Inventor： Liang Dai ,  Kentaro Yamamoto ,  Behnam Sedighi

IPC: H03K3/356 ,  H03M3/00

Abstract: A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.

公开(公告)号：US10439627B2

公开(公告)日：2019-10-08

申请号：US16010117

申请日：2018-06-15

Applicant: Qualcomm Incorporated

Inventor： Sean Baker ,  Dinesh Jagannath Alladi ,  Balasubramanian Sivakumar ,  Kentaro Yamamoto

IPC: H03M1/06 ,  H03M1/00 ,  H04B1/3827

Abstract: An example apparatus is disclosed for alias rejection through charge sharing. The apparatus includes a filter-sampling network, a digital-to-analog converter, and a charge-sharing switch. The filter-sampling network includes a capacitor and a first switch, which is coupled between an input node and the capacitor. The filter-sampling network is configured to connect or disconnect the capacitor to or from the input node via the first switch. The digital-to-analog converter includes a capacitor array and a second switch, which is coupled between the input node and the capacitor array. The capacitor array is coupled between the second switch and a charge-sharing node. The digital-to-analog converter is configured to connect or disconnect the capacitor array to or from the input node via the second switch. The charge-sharing switch is coupled between the charge-sharing node and the capacitor and is configured to connect or disconnect the capacitor to or from the digital-to-analog converter.

公开(公告)号：US20190190529A1

公开(公告)日：2019-06-20

申请号：US16010117

申请日：2018-06-15

Applicant: Qualcomm Incorporated

Inventor： Sean Baker ,  Dinesh Jagannath Alladi ,  Balasubramanian Sivakumar ,  Kentaro Yamamoto

IPC: H03M1/06 ,  H03M1/00

CPC classification number: H03M1/0629 ,  H03M1/002 ,  H03M1/468 ,  H04B1/3827

Abstract: An example apparatus is disclosed for alias rejection through charge sharing. The apparatus includes a filter-sampling network, a digital-to-analog converter, and a charge-sharing switch. The filter-sampling network includes a capacitor and a first switch, which is coupled between an input node and the capacitor. The filter-sampling network is configured to connect or disconnect the capacitor to or from the input node via the first switch. The digital-to-analog converter includes a capacitor array and a second switch, which is coupled between the input node and the capacitor array. The capacitor array is coupled between the second switch and a charge-sharing node. The digital-to-analog converter is configured to connect or disconnect the capacitor array to or from the input node via the second switch. The charge-sharing switch is coupled between the charge-sharing node and the capacitor and is configured to connect or disconnect the capacitor to or from the digital-to-analog converter.

公开(公告)号：US20160056833A1

公开(公告)日：2016-02-25

申请号：US14465650

申请日：2014-08-21

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash Mirhaj ,  Sameer Wadhwa ,  Dinesh Jagannath Alladi ,  Kentaro Yamamoto ,  Xiaoke Wen ,  Masoud Ensafdaran ,  Weihua Chen

IPC: H03M1/72

CPC classification number: H03M1/72 ,  H03M1/0612 ,  H03M1/66 ,  H03M1/804 ,  H03M1/806

Abstract: Reducing signal dependence for a reference voltage of a CDAC includes: splitting a decoupling capacitor into a plurality of capacitors smaller in size than a size of the decoupling capacitor; isolating at least one of the plurality of capacitors from a sampling buffer coupled to the reference voltage during a conversion phase; and supplying an appropriate amount of charge needed to replenish charge drawn by capacitors in the CDAC at each conversion step using a charge pump to pump in a dummy charge to the CDAC so that resulting configurations of the CDAC draw substantially similar amount of charge for each code change of the each conversion step.

Abstract translation: 降低对CDAC的参考电压的信号依赖性包括：将去耦电容器分成尺寸小于去耦电容器的尺寸的多个电容器; 在转换阶段期间将耦合到参考电压的采样缓冲器中的至少一个电容器隔离; 并且在每个转换步骤中使用电荷泵提供在CDAC中由电容器吸收的电荷所需的适当量的电荷，以将虚拟电荷泵送到CDAC，使得CDAC的所得结构为每个代码绘制基本相似的电荷量 更改每个转换步骤。