公开(公告)号：US20190156736A1

公开(公告)日：2019-05-23

申请号：US16120332

申请日：2018-09-03

Applicant: Novatek Microelectronics Corp.

Inventor： Jhih-Siou Cheng ,  Tzong-Honge Shieh ,  Ju-Lin Huang

IPC: G09G3/3208

Abstract: A driver of a display panel is provided. The driver includes a plurality of sensing channels configured to receive a plurality of sensing signals from the display panel via a plurality of sensing lines and output the sensing signals, the sensing channels are coupled to the sensing lines in an arrangement selected from one of a random arrangement and a normal arrangement. The driver further includes a signal convertor coupled to the sensing channels and configured to receive the sensing signals from the sensing channels in a sequence selected from one of a random sequence and a normal sequence.

公开(公告)号：US20200226981A1

公开(公告)日：2020-07-16

申请号：US16830286

申请日：2020-03-26

Applicant: Novatek Microelectronics Corp.

Inventor： Jhih-Siou Cheng ,  Tzong-Honge Shieh ,  Ju-Lin Huang

IPC: G09G3/3258 ,  G06F3/041 ,  G06F3/044 ,  G09G3/3275 ,  G09G3/3208

Abstract: A driver of a display panel is provided. The driver includes a plurality of sensing channels configured to receive a plurality of sensing signals from the display panel via a plurality of sensing lines and output the sensing signals, the sensing channels are coupled to the sensing lines in an arrangement selected from one of a random arrangement and a normal arrangement. The driver further includes a signal convertor coupled to the sensing channels and configured to receive the sensing signals from the sensing channels in a sequence selected from one of a random sequence and a normal sequence.

公开(公告)号：US10297558B1

公开(公告)日：2019-05-21

申请号：US15839813

申请日：2017-12-12

Applicant: Novatek Microelectronics Corp.

Inventor： Tzong-Honge Shieh ,  Po-Hsiang Fang

IPC: G06F3/06 ,  G06F12/00 ,  G11C16/08 ,  G01P21/00 ,  G11C5/00 ,  H03L7/00 ,  G11C16/06 ,  H01L35/00 ,  H01L23/58 ,  H01L21/66 ,  H01L23/525 ,  G11C17/16

Abstract: The disclosure provides a trimming method, a trimming circuitry, and a trimming system for an IC with memory usage reduction. The method is applicable to a system including a tester, a characteristic adjustable circuit, and a trimming circuitry having a characteristic outputting circuit, a data memory, and a trim memory. The method includes the following steps. Under each condition, output signals respectively corresponding to trim settings are received from the characteristic adjustable circuit by the characteristic outputting circuit to obtain output values of the condition, a statistical parameter associated with the output values of the condition is calculated by the tester. The statistical parameter of at least one of the conditions is written into the data memory by the tester. An optimal trim setting of the characteristic adjustable circuit is determined according to the statistical parameters under all the conditions and written into the trim memory by the tester.

公开(公告)号：US20180254758A1

公开(公告)日：2018-09-06

申请号：US15688899

申请日：2017-08-29

Applicant: NOVATEK Microelectronics Corp.

Inventor： Jhih-Siou Cheng ,  Tzong-Honge Shieh

IPC: H03F3/26 ,  H03F3/21 ,  G09G3/36 ,  H03F3/30

Abstract: An operational amplifier includes an output node; an output stage, comprising a plurality of output current paths and a plurality of control nodes, wherein the plurality of control nodes are respectively coupled to the plurality of output current paths, and the plurality of output current paths are coupled to the output node and respectively coupled to a plurality of power supply sources providing different voltages; and a selecting unit, configured to couple an internal output node of the operational amplifier to one of the plurality of control nodes of the output stage.