公开(公告)号：US20240136326A1

公开(公告)日：2024-04-25

申请号：US18399189

申请日：2023-12-28

申请人： Intel Corporation

发明人： Wei LI ,  Edvin CETEGEN ,  Nicholas S. HAEHN ,  Ram S. VISWANATH ,  Nicholas NEAL ,  Mitul MODI

IPC分类号： H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L25/0652 ,  H01L21/486 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16225

摘要： Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

公开(公告)号：US20210195798A1

公开(公告)日：2021-06-24

申请号：US16723865

申请日：2019-12-20

申请人： Intel Corporation

发明人： Nicholas NEAL ,  Nicholas S. HAEHN ,  Je-Young CHANG ,  Kyle ARRINGTON ,  Aaron MCCANN ,  Edvin CETEGEN ,  Ravindranath V. MAHAJAN ,  Robert L. SANKMAN ,  Ken P. HACKENBERG ,  Sergio A. CHAN ARGUEDAS

IPC分类号： H05K7/20 ,  H01L23/367 ,  H01L23/00 ,  H01L23/498

摘要： Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.

公开(公告)号：US20210066162A1

公开(公告)日：2021-03-04

申请号：US16557896

申请日：2019-08-30

申请人： Intel Corporation

发明人： Sergio A. CHAN ARGUEDAS ,  Nicholas S. HAEHN ,  Edvin CETEGEN ,  Nicholas NEAL ,  Jacob VEHONSKY ,  Steve S. CHO ,  Rahul JAIN ,  Antariksh Rao Pratap SINGH ,  Tarek A. IBRAHIM ,  Thomas HEATON ,  Vipul MEHTA

IPC分类号： H01L23/42 ,  H01L23/00

摘要： A device is disclosed. The device includes a substrate, a die on the substrate, a thermal interface material (TIM) on the die, and solder bumps on a periphery of a top surface of the substrate. An integrated heat spreader (IHS) is formed on the solder bumps. The IHS covers the TIM.

公开(公告)号：US20210020532A1

公开(公告)日：2021-01-21

申请号：US16511376

申请日：2019-07-15

申请人： Intel Corporation

发明人： Jacob VEHONSKY ,  Nicholas S. HAEHN ,  Thomas HEATON ,  Steve S. CHO ,  Rahul JAIN ,  Tarek IBRAHIM ,  Antariksh Rao Pratap SINGH ,  Edvin CETEGEN ,  Nicholas NEAL ,  Sergio CHAN ARGUEDAS

IPC分类号： H01L23/16 ,  H01L23/498 ,  H01L23/00 ,  H01L23/367

摘要： Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.

公开(公告)号：US20210020531A1

公开(公告)日：2021-01-21

申请号：US16511360

申请日：2019-07-15

申请人： Intel Corporation

发明人： Edvin CETEGEN ,  Jacob VEHONSKY ,  Nicholas S. HAEHN ,  Thomas HEATON ,  Steve S. CHO ,  Rahul JAIN ,  Tarek IBRAHIM ,  Antariksh Rao Pratap SINGH ,  Nicholas NEAL ,  Sergio CHAN ARGUEDAS ,  Vipul MEHTA

IPC分类号： H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

摘要： Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.