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    GENERATING PRIME NUMBERS
    12.
    发明申请
    GENERATING PRIME NUMBERS 有权

    公开(公告)号：US20220400005A1

    公开(公告)日：2022-12-15

    申请号：US17761712

    申请日：2019-10-16

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Joshua Serratelli Schiffman ,  Thalia May Laing ,  David Plaquin

    IPC: H04L9/08

    Abstract: In an example a method includes retrieving, from a persistent memory, a previously-identified counter value corresponding to an iteration of a prime number generation procedure that previously produced a verified prime number. The method further includes re-generating, using processing circuitry implementing a deterministic prime number calculator and with the previously-identified counter value as an input to the deterministic prime number calculator, the verified prime number.

    Validity of data sets stored in memory
    13.
    发明授权
    Validity of data sets stored in memory 有权

    公开(公告)号：US11354232B2

    公开(公告)日：2022-06-07

    申请号：US16755815

    申请日：2018-01-29

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Jeffrey Kevin Jeansonne ,  Rosilet Retnamoni Braduke ,  David Plaquin ,  Joshua Serratelli Schiffman

    IPC: G06F12/02 ,  G06F12/0831 ,  G06F12/0853 ,  G06F12/0891

    Abstract: An apparatus includes a solid-state a solid-state non-volatile computer memory; and a controller coupled to the memory. The controller to: generate a data set including a tag that indicates that the data set is valid; write the data set into a block of the memory, wherein the block includes multiple addressable locations set to a common first binary value before the write; generate a subsequent data set including a tag that indicates that the subsequent data set is valid; update the tag of the written data set to indicate that the written data set is invalid, wherein the update includes setting an addressable location corresponding to the tag to second binary value different from the first binary value; write the subsequent data set to addressable locations in the block of memory other than the addressable locations of the invalid data set.

    INTERCEPTING DEVICES
    14.
    发明申请
    INTERCEPTING DEVICES 有权

    公开(公告)号：US20220109680A1

    公开(公告)日：2022-04-07

    申请号：US17417129

    申请日：2019-06-24

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： David Plaquin ,  Pierre Belgarric ,  Christopher Ian Dalton ,  Titouan Lazard

    IPC: G06F21/56

    Abstract: In examples, apparatus for detecting malicious or rogue behaviour associated with data packets transmitted between a first device and a second device through a switch is provided, the first device having direct read/write memory access to the second device, in which the apparatus comprises an intercepting device logically intermediate the first device and the switch device to enable the apparatus to analyse the data packets to determine a communication pattern between the first and second devices, compare the communication pattern to a set of expected behaviours for the first device, select, on the basis of the comparison to the set of expected behaviours, a behaviour pattern for the first device, and map the behaviour pattern for the first device to a set of mitigating actions when the behaviour pattern for the first device is symptomatic of a malicious or rogue behaviour.

    Integrated circuit(s) with anti-glitch canary circuit(s)
    15.
    发明授权
    Integrated circuit(s) with anti-glitch canary circuit(s) 有权

    公开(公告)号：US11288405B2

    公开(公告)日：2022-03-29

    申请号：US17058152

    申请日：2018-10-25

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Pierre Belgarric ,  David Plaquin ,  Eugene Cohen ,  Chris R. Gunning

    IPC: G06F21/76 ,  G06F21/60 ,  G06F1/3296 ,  G06K19/073

    Abstract: An IC comprising functional circuit to perform primary functions of the IC is provided. The functional circuit is to enable electrical signals to propagate through it within a timing constraint of the functional circuit. The IC comprises at least one canary circuit used for detecting glitch attacks on the circuit. Electrical signals are to propagate through the canary circuit(s) within a defined timing constraint of the canary circuit(s). The canary circuit is to provide a signal path designed such that in the event of a timing constraint of the functional circuit(s) is violated due to a glitch attack, also the timing constraint of the canary circuit(s) is violated.

    EXECUTING INSTRUCTIONS
    16.
    发明申请
    EXECUTING INSTRUCTIONS 有权

    公开(公告)号：US20210357220A1

    公开(公告)日：2021-11-18

    申请号：US16606762

    申请日：2018-07-31

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Pierre Belgarric ,  Christopher l. Dalton ,  David Plaquin ,  Maugan Villatel ,  Joshua Serratelli Schiffman

    IPC: G06F9/30

    Abstract: Examples include an example computing system comprising a first storage to store executable code, wherein the executable code comprises a plurality of instructions, a second storage to store a first parameter of the executable code, a processing unit to execute each of the instructions of the code, and a monitoring component to, upon execution of each of the instructions of the code by the processing unit, update a second parameter of the code based on that instruction, wherein the monitoring component is to compare the first parameter and the second parameter, and to control execution of further executable code by the processing unit based on the comparison.

    HARDWARE-PROTECTIVE DATA PROCESSING SYSTEMS AND METHODS USING AN APPLICATION EXECUTING IN A SECURE DOMAIN
    18.
    发明申请
    HARDWARE-PROTECTIVE DATA PROCESSING SYSTEMS AND METHODS USING AN APPLICATION EXECUTING IN A SECURE DOMAIN 有权
    硬件保护数据处理系统和使用在安全域中执行的应用程序的方法

    公开(公告)号：US20160125201A1

    公开(公告)日：2016-05-05

    申请号：US14754898

    申请日：2015-06-30

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Maugan Villatel ,  Boris Balacheff ,  Chris I. Dalton ,  David Plaquin ,  Adrian Shaw ,  Simon Kai-Ying Shiu

    IPC: G06F21/62 ,  G06F17/30

    CPC classification number: G06F21/74 ,  G06F9/46 ,  G06F17/30 ,  G06F21/53 ,  G06F21/62 ,  G06F21/6281 ,  G06F21/629

    Abstract: A data processing system supporting a secure domain and a non-secure domain comprises a hardware component, and a processor device having operating modes in the secure domain and non-secure domain, the processor device to execute a secure application in the secure domain. The hardware component has a property having a secure state. The property of the hardware component in the secure state may only be reconfigured responsive to instructions received from the secure domain. The secure application is operative to implement a configuration service to configure the property of the hardware component in the secure state, responsive to a request received from the non-secure domain according to an application programming interface associated with the secure application.

    Abstract translation: 支持安全域和非安全域的数据处理系统包括硬件组件和在安全域和非安全域中具有操作模式的处理器设备，处理器设备在安全域中执行安全应用。 硬件组件具有具有安全状态的属性。 硬件组件处于安全状态的属性可能只能根据从安全域接收到的指令进行重新配置。 响应于根据与安全应用相关联的应用编程接口从非安全域接收的请求，安全应用程序可操作以实现配置服务以配置处于安全状态的硬件组件的属性。

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