公开(公告)号：US20210103429A1

公开(公告)日：2021-04-08

申请号：US16591042

申请日：2019-10-02

Applicant: Facebook, Inc.

Inventor： Krishnakumar Narayanan Nair ,  Anup Ramesh Kadkol ,  Ehsan Khish Ardestani Zadeh ,  Olivia Wu ,  Yuchen Hao ,  Thomas Mark Ulrich ,  Rakesh Komuravelli

IPC: G06F7/487 ,  G06F7/485 ,  G06F17/16 ,  G06N3/02

Abstract: A processor system comprises one or more logic units configured to receive a processor instruction identifying a first floating point number to be multiplied with a second floating point number. The floating point numbers are each decomposed into a group of a plurality of component numbers, wherein a number of bits used to represent each floating point number is greater than a number of bits used to represent any component number in each group of the plurality of component numbers. The component numbers of the first group are multiplied with the component numbers of the second group to determine intermediate multiplication results that are summed together to determine an effective result that represents a result of multiplying the first floating point number with the second floating point number.

公开(公告)号：US20210256363A1

公开(公告)日：2021-08-19

申请号：US16793961

申请日：2020-02-18

Applicant: Facebook, Inc.

Inventor： Krishnakumar Narayanan Nair ,  Rakesh Komuravelli ,  Abdulkadir Utku Diril ,  Ehsan Khish Ardestani Zadeh ,  Yuchen Hao ,  Martin Schatz ,  Thomas Mark Ulrich ,  Olivia Wu ,  Anup Ramesh Kadkol ,  Amin Firoozshahian

IPC: G06N3/063 ,  G06N3/08 ,  G06F9/30 ,  G06F17/16

Abstract: A processor system comprises a first and second group of registers and a hardware channel convolution processor unit. The first group of registers is configured to store data elements of channels of a portion of a convolution data matrix. Each register stores at least one data element from each channel. The second group of registers is configured to store data elements of convolution weight matrices including a separate convolution weight matrix for each channel. Each register stores at least one data element from each convolution weight matrix. The hardware channel convolution processor unit is configured to multiply each data element in the first group of registers with a corresponding data element in the second group of registers and sum together the multiplication results for each specific channel to determine corresponding channel convolution result data elements in a corresponding channel convolution result matrix.