公开(公告)号：US20220137963A1

公开(公告)日：2022-05-05

申请号：US17459935

申请日：2021-08-27

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jeongmin YANG

IPC: G06F9/30 ,  G06F7/544

Abstract: Disclosed are a neural network accelerator and an operating method thereof, which include an instruction analyzer that analyzes a first instruction instructing an operation with respect to a first layer of a neural network algorithm from an external device, a polymorphic operator array including a plurality of operators that performs the operation with respect to the first layer under a control of the instruction analyzer, an interface that communicates with the external device and an external memory under the control of the instruction analyzer, an internal memory, a type converter, a type conversion data mover that stores data received from the external memory through the interface in the internal memory under the control of the instruction analyzer, and an internal type converter that performs a conversion of data stored in the internal memory or data generated by the polymorphic operator array under the control of the instruction analyzer.

公开(公告)号：US20190164037A1

公开(公告)日：2019-05-30

申请号：US16204599

申请日：2018-11-29

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Chan KIM ,  Young-Su KWON ,  Hyun Mi KIM ,  Chun-Gi LYUH ,  Yong Cheol Peter CHO ,  Min-Seok CHOI ,  Jeongmin YANG ,  Jaehoon CHUNG

IPC: G06N3/04 ,  G06N3/08 ,  G06F15/80 ,  G06F17/15

Abstract: In the present invention, by providing an apparatus for processing a convolutional neural network (CNN), including a weight memory configured to store a first weight group of a first layer, a feature map memory configured to store an input feature map where the first weight group is to be applied, an address generator configured to determine a second position spaced from a first position of a first input pixel of the input feature map based on a size of the first weight group, and determine a plurality of adjacent pixels adjacent to the second position; and a processor configured to apply the first weight group to the plurality of adjacent pixels to obtain a first output pixel corresponding to the first position, a memory space may be efficiently used by saving the memory space.

公开(公告)号：US20190164035A1

公开(公告)日：2019-05-30

申请号：US16201871

申请日：2018-11-27

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Young-Su KWON ,  Chan KIM ,  Hyun Mi KIM ,  Jeongmin YANG ,  Chun-Gi LYUH ,  Jaehoon CHUNG ,  Yong Cheol Peter CHO

IPC: G06N3/04

Abstract: A reorganizable neural network computing device is provided. The computing device includes a data processing array unit including a plurality of operators disposed at locations corresponding to a row and a column. One or more chaining paths which transfer the first input data from the operator of the first row of the data processing array to the operator of the second row are optionally formed. The plurality of first data input processors of the computing device transfer the first input data for a layer of the neural network to the operators along rows of the data processing array unit, and the plurality of second data input processors of the computing device transfer the second input data to the operators along the columns of the data processing array.