公开(公告)号：US20160164703A1

公开(公告)日：2016-06-09

申请号：US14633739

申请日：2015-02-27

Applicant: Broadcom Corporation

Inventor： Robert John Stone ,  Howard Frazier

IPC: H04L25/03 ,  H04B10/25 ,  H04L12/26

CPC classification number: H04L25/03057 ,  H04B10/0779 ,  H04B10/0799 ,  H04L25/03159 ,  H04L25/03343

Abstract: A system and method for backchannel closed loop feedback for channel equalization over Ethernet. Closed loop backchannel feedback for real-time transmitter adaptive equalization is provided for a pair of non-ideal duplex communication channels. The real-time transmitter adaptive equalization enables use of low cost relaxed specification transmitter modules at high data rates.

Abstract translation: 一种用于通过以太网进行信道均衡的后向通道闭环反馈的系统和方法。 为一对非理想双工通信信道提供了用于实时发射机自适应均衡的闭环反向信道反馈。 实时发射机自适应均衡使得能够以高数据速率使用低成本的轻松规范发射机模块。

公开(公告)号：US09106570B2

公开(公告)日：2015-08-11

申请号：US14501201

申请日：2014-09-30

Applicant: Broadcom Corporation

Inventor： Burhan Masood ,  Howard Frazier

IPC: H04L12/947 ,  H04L12/761 ,  H04L12/40 ,  G06F13/00 ,  H04L12/931 ,  H04L12/18 ,  H04L12/721

CPC classification number: H04L49/352 ,  G06F13/00 ,  H04L12/18 ,  H04L12/4013 ,  H04L45/16 ,  H04L45/44 ,  H04L49/00 ,  H04L49/25 ,  H04L49/351 ,  Y02D50/10

Abstract: Systems, devices, and methods of implementing 50 Gb/s Ethernet using serializer/deserializer lanes are disclosed. One such device includes circuitry operable to provide a media access control (MAC) interface. The MAC interface is associated with a port having a 50 Gb/s link rate. The device also includes circuitry operable to generate Ethernet frames from data received at the MAC interface and circuitry operable to distribute the Ethernet frames across a group of serial/deserializer (SERDES) lanes associated with the port, the group having size N. The device also includes circuitry operable to transmit the distributed Ethernet frames on each of the SERDES lanes at a 50/N Gb/s rate.

Abstract translation: 公开了使用串行器/解串器通道实现50Gb / s以太网的系统，设备和方法。 一种这样的设备包括可操作以提供媒体访问控制（MAC）接口的电路。 MAC接口与具有50Gb / s链路速率的端口相关联。 该设备还包括可操作以从在MAC接口处接收的数据生成以太网帧的电路，以及可操作以跨过与该端口相关联的一组具有大小为N的组的串/解串行（SERDES）通道组分配以太网帧的电路。该设备还 包括可操作以以50 / N Gb / s速率在每个SERDES通道上传输分布式以太网帧的电路。

公开(公告)号：US20140016637A1

公开(公告)日：2014-01-16

申请号：US13752756

申请日：2013-01-29

Applicant: BROADCOM CORPORATION

Inventor： Burhan Masood ,  Howard Frazier

IPC: H04L12/56

CPC classification number: H04L49/352 ,  G06F13/00 ,  H04L12/18 ,  H04L12/4013 ,  H04L45/16 ,  H04L45/44 ,  H04L49/00 ,  H04L49/25 ,  H04L49/351 ,  Y02D50/10

Abstract: Systems, devices, and methods of implementing 50 Gb/s Ethernet using serializer/deserializer lanes are disclosed. One such device includes circuitry operable to provide a media access control (MAC) interface. The MAC interface is associated with a port having a 50 Gb/s link rate. The device also includes circuitry operable to generate Ethernet frames from data received at the MAC interface and circuitry operable to distribute the Ethernet frames across a group of serializer/deserializer (SERDES) lanes associated with the port, the group having size N. The device also includes circuitry operable to transmit the distributed Ethernet frames on each of the SERDES lanes at a 50/N Gb/s rate.

Abstract translation: 公开了使用串行器/解串器通道实现50Gb / s以太网的系统，设备和方法。 一种这样的设备包括可操作以提供媒体访问控制（MAC）接口的电路。 MAC接口与具有50Gb / s链路速率的端口相关联。 该设备还包括可操作以从在MAC接口处接收的数据生成以太网帧的电路，以及可操作以跨过与该端口相关联的一组具有大小为N的组的串行器/解串行器（SERDES）通道组分配以太网帧的电路。该设备还 包括可以以50 / N Gb / s速率在每个SERDES通道上传输分布式以太网帧的电路。