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公开(公告)号：US11657750B2
公开(公告)日：2023-05-23
申请号：US17289705
申请日：2020-07-08
Inventor： Yu Wang , Yi Zhang , Tingliang Liu , Chang Luo , Tinghua Shang , Huijuan Yang , Yang Zhou , Pengfei Yu , Shun Zhang , Linhong Han , Meng Zhang , Hao Zhang , Xiaofeng Jiang , Huijun Li , Yupeng He , Xin Zhang
IPC: G09G3/20
CPC classification number: G09G3/2074 , G09G2310/0272 , G09G2310/0286 , G09G2330/028
Abstract: A display substrate and a display panel are disclosed. The display substrate includes a base substrate having an active area and a peripheral area surrounding the active area; a plurality of sub-pixels, in the active area; a plurality of first pins and a plurality of second pins located in the peripheral area; a plurality of first array test pins located between the plurality of first pins and the plurality of second pins and respectively electrically coupled to a plurality of array test signal lines; and a plurality of second array test pins located between the plurality of first pins and the plurality of second pins and extending in a direction along a boundary of the active area, wherein the plurality of first array test pins are located on at least one side of the plurality of second array test pins in the direction along the boundary of the active area.
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公开(公告)号：US20220399427A1
公开(公告)日：2022-12-15
申请号：US17606424
申请日：2020-12-25
Inventor： Tinghua Shang , Huijuan Yang , Tingliang Liu , Yi Zhang , Hao Zhang , Lulu Yang , Yang Zhou , Xiaofeng Jiang
IPC: H01L27/32 , G09G3/3233
Abstract: An array substrate is provided. A first virtual line and a second virtual line respectively cross over a first voltage supply line, a second voltage supply line, and a third voltage supply line. The first voltage supply line, the second voltage supply line, and the third voltage supply line respectively include a first voltage supply line portion, a second voltage supply line portion, and a third voltage supply line portion, respectively between the first virtual line and the second virtual line. An orthographic projection of a third anode of a third light emitting element on a base substrate completely covers an orthographic projection of the third voltage supply line portion on the base substrate. The third voltage supply line portion has a line width greater than a line width of the first voltage supply line portion, and greater than a line width of the second voltage supply line portion.
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13.发明授权公开(公告)号：US11387310B2
公开(公告)日：2022-07-12
申请号：US16963683
申请日：2019-10-14
Inventor： Huijuan Yang , Tingliang Liu , Gen Li , Yang Zhou
Abstract: An array substrate and a display panel are disclosed. The array substrate includes: a base substrate including a display region and a peripheral region; a plurality of sub-pixels in the display region; a plurality of data lines in the display region; a plurality of first power lines in the display region; a plurality of data lead lines in the peripheral region; a plurality of selection switches in the peripheral region; a plurality of data signal input lines in the peripheral region; a first power bus in the peripheral region; and a plurality of connection portions electrically connecting the first power bus to the plurality of first power lines, respectively. The plurality of connection portions include a plurality of first connection portions and a plurality of second connection portions on both sides of the plurality of first connection portions.
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公开(公告)号：US12236845B2
公开(公告)日：2025-02-25
申请号：US17907936
申请日：2021-09-29
IPC: G09G3/32 , H01L25/075 , H01L25/16 , H01L27/12 , H01L33/62
Abstract: A display substrate includes a first voltage line, an alternating current signal line and a second voltage line arranged on a substrate, the substrate includes a display region and a non-display region; the display substrate further includes a first conductive layer, a first insulation layer and a second conductive layer laminated one on another on the substrate, the first voltage line and the alternating current signal line are arranged on the first conductive layer, and the second voltage line is arranged on the second conductive layer; the first voltage line is lapped onto the second voltage line through a first groove penetrating through the first insulation layer; and an orthogonal projection of the second voltage line onto the substrate overlaps an orthogonal projection of the alternating current signal line onto the substrate at an overlapping region.
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公开(公告)号：US12219836B2
公开(公告)日：2025-02-04
申请号：US18407506
申请日：2024-01-09
Inventor： Maoying Liao , Yang Zhou , Xin Zhang , Huijuan Yang
IPC: H10K59/131 , G06F3/041 , G09G3/3258 , G09G3/3266 , H01L27/12 , H10K50/80 , H10K59/121 , H10K59/124
Abstract: An array substrate is provided. The array substrate includes a node connecting line in a same layer as a respective one of the plurality of voltage supply lines, connected to a first capacitor electrode through a first via, and connected to a semiconductor material layer through a second via; and an interference preventing block in a same layer as the second capacitor electrode. Along the first direction, a portion of the node connecting line at a position connecting to the semiconductor material layer through the second via is spaced apart from a first adjacent data line by a first arm, and is spaced apart from a second adjacent data line by a second arm. An orthographic projection of a respective one of the plurality of voltage supply lines on the base substrate substantially covers at least 30% of an orthographic projection of the second arm on the base substrate.
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Patent Agency Ranking
公开(公告)号：US12114545B2
公开(公告)日：2024-10-08
申请号：US17419763
申请日：2020-09-11
Inventor： Huijuan Yang , Yang Zhou , Xiaofeng Jiang , Tinghua Shang , Gen Li
IPC: H10K59/65 , G09G3/20 , G09G3/3233 , H01L27/32 , H10K59/121 , H10K59/131
CPC classification number: H10K59/131 , H10K59/1213 , H10K59/1216 , H10K59/65 , G09G3/2074 , G09G3/3233 , G09G2300/0426 , G09G2300/0842
Abstract: A display substrate and a display apparatus. In the display substrate, the first signal line sequentially passes through the first display region, the opening peripheral region and the second display region along a first direction, and includes a first lead portion and a first winding portion that are in the opening peripheral region and connected to each other; the first winding portion partially surrounds the opening; the second signal line provides a second display signal to the pixel array, passes through the peripheral region of the opening along a second direction intersecting with the first direction, includes a second winding portion in the peripheral region of the opening and partially surrounds the opening. The first lead portion and the second signal line have a first overlapping region, and the first winding portion and the second winding portion have a second overlapping region.
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公开(公告)号：US12029084B2
公开(公告)日：2024-07-02
申请号：US17312085
申请日：2020-12-28
Inventor： Linhong Han , Xiaofeng Jiang , Youngyik Ko , Yi Zhang , Yang Zhou , Yu Wang , Shikai Qin , Tingliang Liu , Haigang Qing , Shun Zhang
IPC: H10K59/131 , H10K50/844 , H10K59/12 , H10K71/00
CPC classification number: H10K59/131 , H10K50/844 , H10K71/00 , H10K59/1201
Abstract: The embodiments of the present disclosure disclose a display substrate, a fabrication method thereof and a display apparatus. The display substrate includes: a base substrate, including a display region and a bonding region located on at least one side of the display region; a conductive layer, located on the base substrate and in the bonding region and including a plurality of first conducive terminals; and an insulation protection layer, located on one side, facing away from the base substrate, of the conductive layer, and having hollow regions and pattern regions, where the hollow regions cover the first conductive terminals, and the pattern regions cover gaps among the plurality of first conductive terminals.
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公开(公告)号：US12016217B2
公开(公告)日：2024-06-18
申请号：US17265293
申请日：2020-04-14
Inventor： Linhong Han , Tinghua Shang , Pengfei Yu , Shun Zhang , Yang Zhou
IPC: H10K59/131 , H01L23/00 , H01L25/18 , H10K59/88 , H10K77/10 , H10K102/00
CPC classification number: H10K59/131 , H01L24/05 , H01L24/06 , H01L24/32 , H01L25/18 , H01L2224/05548 , H01L2224/0603 , H01L2224/32145 , H01L2224/32225 , H10K59/88 , H10K77/111 , H10K2102/311
Abstract: The present disclosure provides a display panel and a display device. The display panel includes: a display substrate, an IC chip, and a circuit board. The display substrate includes a first bonding portion including a first detection pin and a second detection pin, a second bonding portion connected to the first bonding portion and including a first connection pin and second connection pin which are connected by a connection wire included by the circuit board, a first connection line connecting the first detection pin to the first connection pin and including a first crack detection line, and a second connection line connecting the first detection pin to the second connection pin. The IC chip is bonded to the first bonding portion and configured to determine cracks on an edge of the display substrate according to electric signals of the first detection pin and the second detection pin.
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公开(公告)号：US20240196683A1
公开(公告)日：2024-06-13
申请号：US18586988
申请日：2024-02-26
Inventor： Tinghua Shang , Haigang Qing , Yi Zhang , Tingliang Liu , Yu Wang , Yang Zhou
IPC: H10K59/131 , G09G3/3233 , H10K59/12 , H10K71/00
CPC classification number: H10K59/1315 , G09G3/3233 , H10K71/00 , G09G2300/0426 , G09G2300/0842 , G09G2310/08 , G09G2320/0209 , H10K59/1201
Abstract: A display substrate, a method for manufacturing the display substrate, and a display device. In the display substrate, the first sub-pixel and the second sub-pixel each include: a power signal line pattern, at least part of the power signal line pattern extends along the second direction; and a power compensation pattern, at least part of the power compensation pattern extends along the first direction, the power signal line pattern and the power compensation pattern are both located on a side of the first data line pattern and the second data line pattern close to the substrate; the power compensation pattern is electrically connected to the power signal line pattern and a power signal line pattern in an adjacent sub-pixel along the first direction.
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公开(公告)号：US20240179948A1
公开(公告)日：2024-05-30
申请号：US17773600
申请日：2021-07-30
Inventor： Da Zhou , Jianbo Wang , Taoran Zhang , Li Huang , Yang Zhou
IPC: H10K59/122 , H10K59/131
CPC classification number: H10K59/122 , H10K59/131
Abstract: An array substrate includes a planarization layer; an anode material layer on the planarization layer and in a peripheral area of the array substrate; and a plurality of gas releasing vias extending through the anode material layer configured to release gas in the planarization layer during a fabrication process. An aperture size of a first respective gas releasing via in a first region is smaller than an aperture size of a second respective gas releasing via in a second region.
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