公开(公告)号：US3568162A

公开(公告)日：1971-03-02

申请号：US3568162D

申请日：1968-09-27

Applicant: BELL TELEPHONE LABOR INC

Inventor： TOY WING N

IPC: G06F5/01 ,  G06F9/308 ,  G06F5/00

CPC classification number: G06F9/30018 ,  G06F5/015

Abstract: The contents of a selected one of plural general purpose registers in a data processing system are selectably coupled through first-ZERO-detecting logic to modify the contents of a buffer register. The modification takes the form of setting to the ONE state the bit position in the buffer register corresponding to the low order ZERO position of the originating register contents and resetting any lower bit positions to ZERO. The modified contents of the buffer register are then coupled back to the one originating register. Program-controlled circuits perform, in selectable sequences, the normal store and reset types of operations on the originating registers in the course of the movement of information to the ZERO detecting logic and back again. Illustrative processing functions that can be selected in this fashion include marking a low order ZERO and incrementing the contents of the originating register. Another first-ZEROdetecting logic circuit is employed to control the operation of a rotate circuit in cooperation with the first-mentioned ZERO detecting logic to permit both ZERO detectors to have a data bit width which is much smaller than the processor word size.

公开(公告)号：US3555255A

公开(公告)日：1971-01-12

申请号：US3555255D

申请日：1968-08-09

Applicant: BELL TELEPHONE LABOR INC

Inventor： TOY WING N

IPC: G06F11/10 ,  G06F11/28 ,  G06F11/08

CPC classification number: G06F11/10 ,  G06F11/28

Abstract: Outputs of the ordered stages of a register are applied to a first-ZERO-detecting logic and outputs of the latter are used to predict what parity state should prevail in registered information after a predetermined operation has been performed on the registered information. Illustrative predetermined operations are high speed counting and marking a low order bit of a predetermined type. The first-ZERO-detecting logic is actuated simultaneously with the initiation of the operation to be performed on the registered information and is utilized in the performance of that operation. Predicted parity is then compared with a parity indication computed after the operation has been completed to evaluate the accuracy with which the operation was carried out.

公开(公告)号：US3428945A

公开(公告)日：1969-02-18

申请号：US3428945D

申请日：1965-05-20

Applicant: BELL TELEPHONE LABOR INC

Inventor： TOY WING N

IPC: G06F11/08 ,  G08C25/00

CPC classification number: G06F11/085