公开(公告)号：US20150019824A1

公开(公告)日：2015-01-15

申请号：US13940525

申请日：2013-07-12

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Perumal R. Subramoniam ,  Prashant Jain

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/1027 ,  G06F2212/6022 ,  G06F2212/654

Abstract: An apparatus for processing cache requests in a computing system is disclosed. The apparatus may include a pending request buffer and a control circuit. The pending request buffer may include a plurality of buffer entries. The control circuit may be coupled to the pending request buffer and may be configured to receive a request for a first cache line from a pre-fetch engine, and store the received request in an entry of the pending request buffer. The control circuit may be further configured to receive a request for a second cache line from a processor, and store the request received from the processor in the entry of the pending request buffer in response to a determination that the second cache line is the same as the first cache line.

Abstract translation: 公开了一种用于处理计算系统中的缓存请求的装置。 该装置可以包括未决请求缓冲器和控制电路。 待决请求缓冲器可以包括多个缓冲器条目。 控制电路可以耦合到未决请求缓冲器，并且可以被配置为从预取引擎接收对第一高速缓存行的请求，并将接收到的请求存储在待处理请求缓冲器的条目中。 控制电路还可以被配置成从处理器接收对第二高速缓存线的请求，并且响应于确定第二高速缓存行与第二高速缓存行相同的存储将处理器接收到的请求存储在等待请求缓冲器的条目中 第一个缓存行。

公开(公告)号：US20160055099A1

公开(公告)日：2016-02-25

申请号：US14929645

申请日：2015-11-02

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Gerard R. Williams, III ,  Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Hari S. Kannan ,  Prashant Jain

IPC: G06F12/12

CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/127 ,  G06F2212/1021

Abstract: A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory.

公开(公告)号：US20150026404A1

公开(公告)日：2015-01-22

申请号：US13946327

申请日：2013-07-19

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Gerard R. Williams, III ,  Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Hari S. Kannan ,  Prashant Jain

IPC: G06F12/08

CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/127 ,  G06F2212/1021

Abstract: A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory.

Abstract translation: 用于从高速缓冲存储器中逐出高速缓存行的机制包括首先选择驱逐一组无效高速缓存行的最近最少使用的高速缓存行。 如果所有高速缓存行都有效，则选择驱逐，一组高速缓存行的最近最少使用的高速缓存行，其中该高速缓存行组中的高速缓存行也不存储在诸如L1高速缓存的更高级高速缓冲存储器中 。 最后，如果所有高速缓存行都是有效的，并且没有非包含的高速缓存行，则选择驱逐存储在高速缓冲存储器中的最近最少使用的高速缓存行。