公开(公告)号：US20230094639A1

公开(公告)日：2023-03-30

申请号：US17946213

申请日：2022-09-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rex Eldon MCCRARY

IPC: G06F9/48 ,  G06F9/38 ,  G06F12/0831 ,  G06F9/54 ,  G06F9/30

Abstract: A first processing unit such as a graphics processing unit (GPU) pipelines that execute commands and a scheduler to schedule one or more first commands for execution by one or more of the pipelines. The one or more first commands are received from a user mode driver in a second processing unit such as a central processing unit (CPU). The scheduler schedules one or more second commands for execution in response to completing execution of the one or more first commands and without notifying the second processing unit. In some cases, the first processing unit includes a direct memory access (DMA) engine that writes blocks of information from the first processing unit to a memory. The one or more second commands program the DMA engine to write a block of information including results generated by executing the one or more first commands.

公开(公告)号：US20220091847A1

公开(公告)日：2022-03-24

申请号：US17029841

申请日：2020-09-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexander Fuad ASHKAR ,  Harry J. WISE ,  Rex Eldon MCCRARY ,  Hans FERNLUND

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/54 ,  G06F13/16

Abstract: In response to executing a specified command packet, a processing unit prefetches commands stored at an indirect buffer a command queue for execution, prior to executing a command that initiates execution of the commands stored at the indirect buffer. By prefetching the data prior to executing the indirect buffer execution command, the processing unit reduces delays in processing the commands stored at the indirect buffer.

公开(公告)号：US20210191771A1

公开(公告)日：2021-06-24

申请号：US16721456

申请日：2019-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rex Eldon MCCRARY

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/30 ,  G06F9/54 ,  G06F12/0831

Abstract: A first processing unit such as a graphics processing unit (GPU) pipelines that execute commands and a scheduler to schedule one or more first commands for execution by one or more of the pipelines. The one or more first commands are received from a user mode driver in a second processing unit such as a central processing unit (CPU). The scheduler schedules one or more second commands for execution in response to completing execution of the one or more first commands and without notifying the second processing unit. In some cases, the first processing unit includes a direct memory access (DMA) engine that writes blocks of information from the first processing unit to a memory. The one or more second commands program the DMA engine to write a block of information including results generated by executing the one or more first commands.

公开(公告)号：US20200379792A1

公开(公告)日：2020-12-03

申请号：US16427407

申请日：2019-05-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexander Fuad ASHKAR ,  Rakan KHRAISHA ,  Rex Eldon MCCRARY ,  Harry J. WISE

IPC: G06F9/455

Abstract: A processing unit employs microcode wherein the jump table associated with the microcode is embedded in the microcode itself. When the microcode is compiled based on a set of programmer instructions, the compiler prepares the jump table for the microcode and stores the jump table in the same file or other storage unit as the microcode. When the processing unit is initialized to execute a program, such as an operating system, the processing unit retrieves the microcode corresponding to the program from memory, stores the microcode in a cache or other memory module for execution, and automatically loads the embedded jump table from the microcode to a specified set of jump table registers, thereby preparing the processing unit to process received packets.