公开(公告)号：US07570526B2

公开(公告)日：2009-08-04

申请号：US11617226

申请日：2006-12-28

申请人： Jung Chul Han

发明人： Jung Chul Han

IPC分类号： G11C29/00

CPC分类号： G11C17/18 ,  G11C29/76 ,  G11C29/802 ,  G11C2229/723

摘要： A memory device includes a main memory cell having a plurality of first memory cells for storing data, wherein a special block for storing a column address corresponding to a first memory cell having at least one failure is disposed in a part of area of the main memory cell; a start address block configured to store address information initiated by the special block of the main memory cell; and a repair information block configured to provisionally store the column address stored in the special block, and to output a repair controlling signal when operating the memory device.

摘要翻译： 一种存储装置包括具有多个用于存储数据的第一存储单元的主存储单元，其中存储与具有至少一个故障的第一存储单元对应的列地址的特殊块设置在主存储器的一部分区域中 细胞; 开始地址块，被配置为存储由所述主存储单元的特殊块发起的地址信息; 以及修复信息块，被配置为临时存储存储在特殊块中的列地址，并且在操作存储器件时输出修复控制信号。

公开(公告)号：US20090290418A1

公开(公告)日：2009-11-26

申请号：US12469346

申请日：2009-05-20

申请人： Jung Chul HAN

发明人： Jung Chul HAN

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2216/14

摘要： A method of verifying a program operation in a non-volatile memory device includes performing a program operation, verifying whether or not each of a plurality of program target memory cells is programmed to a voltage higher than a verifying voltage, counting a number of fail status bits in response to determining that a fail status memory cell is not programmed with a voltage higher than the verifying voltage based on the verified result, and setting data so that a plurality of page buffers each output a pass signal when the number of the fail status bits is smaller than a number of error correction code (ECC) processing bits.

摘要翻译： 一种验证非易失性存储器件中的程序操作的方法包括执行程序操作，验证多个程序目标存储器单元中的每一个是否被编程为高于验证电压的电压，对故障状态数进行计数 响应于基于验证结果确定故障状态存储单元未被编程为具有高于验证电压的电压的位，并且设置数据使得当故障状态的数量时多个页缓冲器输出通过信号 比特小于多个纠错码（ECC）处理比特。

公开(公告)号：US08456912B2

公开(公告)日：2013-06-04

申请号：US13104475

申请日：2011-05-10

申请人： Jung-Chul Han ,  Seong-Je Park

发明人： Jung-Chul Han ,  Seong-Je Park

IPC分类号： G11C11/34

CPC分类号： G11C16/3454 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10

摘要： A nonvolatile memory device includes a page region including a plurality of normal cells and a plurality of auxiliary cells, a detecting unit configured to output a pass signal when at least one cell is programmed with a voltage higher than a reference voltage among program target cells of the page region, a count storing unit configured to store a count in the plurality of auxiliary cells during a first program operation for the page region, wherein the count indicates a total number of program pulses applied to the at least one cell until the pass signal is outputted from the detecting unit, and a voltage setting unit configured to set a program start voltage for a second program operation of the page region based on the count stored in the plurality of auxiliary cells.

摘要翻译： 非易失性存储器件包括包括多个正常单元和多个辅助单元的页面区域，检测单元，被配置为当至少一个单元被编程为高于参考电压的电压时，输出通过信号， 所述页面区域，计数存储单元，被配置为在所述页面区域的第一编程操作期间在所述多个辅助单元中存储计数，其中所述计数指示施加到所述至少一个单元的编程脉冲的总数，直到所述通过信号 从所述检测单元输出，以及电压设定单元，其被配置为基于存储在所述多个辅助单元中的计数来设置用于所述页面区域的第二编程操作的程序开始电压。

公开(公告)号：US20120198132A1

公开(公告)日：2012-08-02

申请号：US13188685

申请日：2011-07-22

申请人： Jung Chul HAN

发明人： Jung Chul HAN

IPC分类号： G06F12/00

CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C16/32

摘要： A non-volatile memory system includes a memory area including one or more non-volatile memory apparatuses, and a controller includes a buffer for storing program data, and is configured to transmit a program command and the program data to the memory area and delete the program data stored in the buffer as a program operation is started in the memory area.

摘要翻译： 非易失性存储器系统包括包括一个或多个非易失性存储装置的存储器区域，并且控制器包括用于存储程序数据的缓冲器，并且被配置为将程序命令和程序数据发送到存储区域并删除 作为程序操作存储在缓冲器中的程序数据在存储器区域中开始。

公开(公告)号：US08208308B2

公开(公告)日：2012-06-26

申请号：US12796209

申请日：2010-06-08

申请人： Jung Chul Han ,  Seong Je Park

发明人： Jung Chul Han ,  Seong Je Park

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C2216/14

摘要： A method of programming a nonvolatile memory device includes an initial data setting step of inputting data for program inhibition to a first latch of a page buffer to which memory cells to be programmed with a second threshold voltage distribution are coupled, a first program and verification step of performing program and verification operations, a first data setting step of, when a program pulse is supplied more than N times (where N is a natural number), inputting data for performing a program operation to the first latch of the page buffer to which the memory cells to be programmed with the second threshold voltage distribution are coupled, and a second program and verification step of performing program and verification operations.

摘要翻译： 一种对非易失性存储器件进行编程的方法包括：初始数据设置步骤，用于将用于编程禁止的数据输入到第二阈值电压分布所要编程的存储器单元的页缓冲器的第一锁存器，第一程序和验证步骤 执行程序和验证操作的第一数据设置步骤，当程序脉冲被提供多于N次（其中N是自然数）时，将用于执行编程操作的数据输入到页缓冲器的第一锁存器 将要用第二阈值电压分布编程的存储器单元耦合，以及执行程序和验证操作的第二程序和验证步骤。

公开(公告)号：US08174903B2

公开(公告)日：2012-05-08

申请号：US12790191

申请日：2010-05-28

申请人： Jung Chul Han ,  Seong Je Park

发明人： Jung Chul Han ,  Seong Je Park

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427 ,  G11C16/3454

摘要： A method of operating a nonvolatile memory device, including a memory cell array, which further includes a drain select transistor, a memory cell string, and a source select transistor coupled between a bit line and a source line, where the method includes precharging the bit line, setting the memory cell string in a ground voltage state, coupling the memory cell string and the bit line together and supplying a read voltage or a verification voltage to a selected memory cell of the memory cell string, and coupling the memory cell string and the source line together in order to change a voltage level of the bit line in response to a threshold voltage of the selected memory cell.

摘要翻译： 一种操作包括存储单元阵列的非易失性存储器件的方法，其还包括漏极选择晶体管，存储单元串和耦合在位线和源极线之间的源极选择晶体管，其中所述方法包括对所述位进行预充电 将存储单元串设置为接地电压状态，将存储单元串和位线耦合在一起，并将读取电压或验证电压提供给存储单元串的选定存储单元，并将存储单元串和 源极线一起以响应于所选存储器单元的阈值电压来改变位线的电压电平。

公开(公告)号：US08174896B2

公开(公告)日：2012-05-08

申请号：US12647593

申请日：2009-12-28

申请人： Kyu Hee Lim ,  Seong Je Park ,  Jung Chul Han

发明人： Kyu Hee Lim ,  Seong Je Park ,  Jung Chul Han

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2216/14

摘要： A nonvolatile memory device comprises a page buffer unit, a counter, a program pulse application number storage unit, and a program start voltage setting unit. The page buffer is configured to output a 1-bit pass signal when a cell programmed to exceed a reference voltage, from among target program cells included in a single page, exists. The counter is configured to count a number of program pulses applied to determine a program pulse application number. The program pulse application number storage unit is configured to store a number of program pulses applied until the 1-bit pass signal is received during a program operation for a first page. The program start voltage setting unit is configured to set a program start voltage for a second page based on the stored program pulse application number.

摘要翻译： 非易失性存储器件包括页缓冲器单元，计数器，编程脉冲应用次数存储单元和程序启动电压设置单元。 页缓冲器被配置为当编程为超过包括在单页中的目标程序单元中的参考电压的单元存在时，输出1位通过信号。 计数器配置为对用于确定编程脉冲应用编号的程序脉冲数进行计数。 编程脉冲应用次数存储单元被配置为存储施加的编程脉冲数，直到在第一页的编程操作期间接收到1位通过信号。 程序启动电压设定单元被配置为基于存储的程序脉冲应用程序号来设置第二页的程序启动电压。

公开(公告)号：US20100329020A1

公开(公告)日：2010-12-30

申请号：US12796209

申请日：2010-06-08

申请人： Jung Chul HAN ,  Seong Je Park

发明人： Jung Chul HAN ,  Seong Je Park

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C2216/14

摘要： A method of programming a nonvolatile memory device includes an initial data setting step of inputting data for program inhibition to a first latch of a page buffer to which memory cells to be programmed with a second threshold voltage distribution are coupled, a first program and verification step of performing program and verification operations, a first data setting step of, when a program pulse is supplied more than N times (where N is a natural number), inputting data for performing a program operation to the first latch of the page buffer to which the memory cells to be programmed with the second threshold voltage distribution are coupled, and a second program and verification step of performing program and verification operations.

摘要翻译： 一种对非易失性存储器件进行编程的方法包括：初始数据设置步骤，用于将用于编程禁止的数据输入到第二阈值电压分布所要编程的存储器单元的页缓冲器的第一锁存器，第一程序和验证步骤 执行程序和验证操作的第一数据设置步骤，当程序脉冲被提供多于N次（其中N是自然数）时，将用于执行编程操作的数据输入到页缓冲器的第一锁存器 将要用第二阈值电压分布编程的存储器单元耦合，以及执行程序和验证操作的第二程序和验证步骤。

公开(公告)号：US20100226171A1

公开(公告)日：2010-09-09

申请号：US12650613

申请日：2009-12-31

申请人： Jung Chul HAN

发明人： Jung Chul HAN

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3418 ,  G11C11/5628

摘要： A method of programming a nonvolatile memory device includes receiving a program command, performing program and verification operations in response to each of a number of program pulse, and performing an n number of program operations, where n is a positive integer and at least one verification operation for the n program operations has been omitted.

摘要翻译： 一种编程非易失性存储器件的方法包括接收程序命令，响应于多个编程脉冲中的每一个执行程序和验证操作，以及执行n个程序操作，其中n是正整数和至少一个验证 已经省略了对n程序操作的操作。

公开(公告)号：US20100182844A1

公开(公告)日：2010-07-22

申请号：US12472678

申请日：2009-05-27

申请人： Jung Chul HAN

发明人： Jung Chul HAN

IPC分类号： G11C16/06

CPC分类号： G11C16/3454

摘要： In an operating method in a read or verification operation of a nonvolatile memory device, selected bit lines are precharged to a logic high level and, at the same time, unselected bit lines are discharged to a logic low level. The selected and unselected bit lines are connected to respective memory cell strings and, concurrently, word lines are supplied with a pass voltage. The connection between the selected and unselected bit lines and the respective memory cell strings is shut off and, concurrently, a selected word line is supplied with a ground voltage. The selected and unselected bit lines and the respective memory cell strings are coupled together and, concurrently, a selected word line is supplied with a reference voltage and an unselected word line is supplied with the pass voltage.

摘要翻译： 在非易失性存储器件的读取或验证操作中的操作方法中，所选择的位线被预充电到逻辑高电平，并且同时未选择的位线被放电到逻辑低电平。 所选择的和未选择的位线被连接到相应的存储单元串，同时，字线被提供有通过电压。 所选择的和未选择的位线与各个存储单元串之间的连接被切断，同时，所选择的字线被提供有接地电压。 所选择的和未选择的位线和相应的存储器单元串耦合在一起，并且同时将选定的字线提供给参考电压，并且向未选择的字线提供通过电压。