公开(公告)号：US20140203401A1

公开(公告)日：2014-07-24

申请号：US13748768

申请日：2013-01-24

Applicant: QUALCOMM INCORPORATED

Inventor： Xia Li ,  Bin Yang

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L28/88 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metal-on-Metal (MoM) capacitors having laterally displaced layers and related systems and methods are disclosed. In one embodiment, a MoM capacitor includes a plurality of vertically stacked layers that are laterally displaced relative to one another. Lateral displacement of the layers minimizes cumulative surface process variations making a more reliable and uniform capacitor.

Abstract translation: 公开了具有横向移位层的金属对金属（MoM）电容器及相关系统和方法。 在一个实施例中，MoM电容器包括相对于彼此横向移位的多个垂直堆叠的层。 层的横向位移最小化累积的表面处理变化，从而形成更可靠和更均匀的电容器。

公开(公告)号：US20140138793A1

公开(公告)日：2014-05-22

申请号：US13684059

申请日：2012-11-21

Applicant: QUALCOMM INCORPORATED

Inventor： PR Chidambaram ,  Bin Yang

IPC: H01L49/02

CPC classification number: H01L27/0629 ,  H01L23/5223 ,  H01L23/5228 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacito includes depositing a first middle of line (MOL) conductive layer over a shallow trench isolation (STI) region of a semiconductor substrate. The first MOL conductive layer provides a first plate of the MIM capacitor as well as a first set of local interconnects to source and drain regions of a semiconductor device. The method also includes depositing an insulator layer on the first MOL conductive layer as a dielectric layer of the MIM capacitor. The method further includes depositing a second MOL, conductive layer on the insulator layer as a second plate of the MIM capacitor.

Abstract translation: 一种用于制造金属 - 绝缘体 - 金属（MIM）电容的方法，包括在半导体衬底的浅沟槽隔离（STI）区域上沉积第一中间线（MOL）导电层。 第一MOL导电层提供MIM电容器的第一板以及到半导体器件的源极和漏极区域的第一组局部互连。 该方法还包括在第一MOL导电层上沉积绝缘体层作为MIM电容器的电介质层。 该方法还包括在MIM电容器的第二板上沉积在绝缘体层上的第二MOL导电层。

公开(公告)号：US20140092523A1

公开(公告)日：2014-04-03

申请号：US13799079

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  PR Chidambaram ,  Lixin Ge ,  Bin Yang ,  Jihong Choi

IPC: H01G4/012 ,  H01G4/005 ,  H01G4/38

CPC classification number: H01G4/012 ,  H01G4/005 ,  H01G4/10 ,  H01G4/33 ,  H01G4/38 ,  H01L28/86

Abstract: An orthogonal finger capacitor includes a layer having an anode bone frame adjacent a cathode bone frame, the anode bone frame having a first portion extending along an axis and a second portion extending perpendicular to the axis. A set of anode fingers extends from the first portion. A set of cathode fingers extends from the cathode bone frame, interdigitated with the set of anode fingers. An overlaying layer has another anode bone frame having a first portion parallel to the axis and a perpendicular second portion. A via couples the overlaying anode bone frame to the underlying anode bone frame. The via is located where the first portion of the overlaying anode bone frame overlaps the second portion of the underlying anode bone frame or, optionally, where the second portion of the overlying anode bone frame overlaps the first portion of the underlying anode bone frame.

Abstract translation: 正交手指电容器包括具有邻近阴极骨架的阳极骨架的层，阳极骨架具有沿轴线延伸的第一部分和垂直于轴线延伸的第二部分。 一组阳极指从第一部分延伸。 一组阴极指状物从阴极骨框架延伸，与一组阳极指状物交叉。 覆盖层具有另一阳极骨架，其具有平行于轴线的第一部分和垂直的第二部分。 A通孔将覆盖的阳极骨框架耦合到下面的阳极骨框架。 通孔位于覆盖阳极骨框架的第一部分与下面的阳极骨框架的第二部分重叠的位置，或者可选地，其中上覆的阳极骨架的第二部分与下面的阳极骨架的第一部分重叠。

公开(公告)号：US20140036578A1

公开(公告)日：2014-02-06

申请号：US13741869

申请日：2013-01-15

Applicant: QUALCOMM INCORPORATED

Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Bin Yang ,  Choh Fei Yeap

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C11/419

Abstract: Methods and apparatuses for static memory cells. A static memory cell may include a first pass gate transistor including a first back gate node and a second pass gate transistor including a second back gate node. The static memory cell may include a first pull down transistor including a third back gate node and a second pull down transistor including a fourth back gate node. The source node of the first pull down transistor, source node of the second pull down transistor, and first, second, third, and fourth back gate nodes are electrically coupled to each other to form a common node.

Abstract translation: 静态存储单元的方法和装置。 静态存储单元可以包括第一栅极晶体管，其包括第一背栅极节点和包括第二后栅极节点的第二栅极晶体管。 静态存储单元可以包括包括第三后栅极节点的第一下拉晶体管和包括第四背栅极节点的第二下拉晶体管。 第一下拉晶体管的源节点，第二下拉晶体管的源节点以及第一，第二，第三和第四后门节点彼此电耦合以形成公共节点。