公开(公告)号：US5793616A

公开(公告)日：1998-08-11

申请号：US829152

申请日：1997-03-31

Applicant: Mark S. Aubuchon ,  John C. Barker

Inventor： Mark S. Aubuchon ,  John C. Barker

IPC: G06F1/18 ,  H05K1/14 ,  H05K7/14

CPC classification number: G06F1/184 ,  H05K1/14 ,  H05K7/1429 ,  Y10S439/928

Abstract: A computer system includes a chassis having a generally planar floor plate; a first generally planar motherboard having circuitry thereon mounted on the floor plate; at least one riser board connected to the first motherboard to extend generally orthogonally upwardly therefrom, the riser board having an upper edge oriented generally parallel to and above the plane of the first motherboard, and being provided with electrical circuit contacts along the upper edge; and a second generally planar motherboard connected to and at least partly supported by the riser board, the second motherboard being positioned adjacent the upper edge of the riser board, the second motherboard having circuitry thereon electrically connected to the electrical circuit contacts along the upper edge of the riser board.

Abstract translation: 计算机系统包括具有大致平面的底板的底盘; 第一大致平面的主板，其上有电路，其上安装在地板上; 至少一个连接到所述第一母板的提升板基本上从所述第一母板正交地向上延伸，所述提升板具有大致平行于所述第一母板的平面并且高于所述第一母板的平面的上边缘，并且沿着所述上边缘设置有电路触点; 以及连接到所述提升板并且至少部分地由所述提升板基板支撑的第二大致平面的主板，所述第二主板被定位成与所述提升板的上边缘相邻，所述第二主板具有电路，所述第二主板具有电路，其沿着所述提升板的上边缘电连接到所述电路触点 提升板。

公开(公告)号：US5791753A

公开(公告)日：1998-08-11

申请号：US705402

申请日：1996-08-29

Applicant: David M. Paquin

Inventor： David M. Paquin

IPC: G06F1/18 ,  H05K7/14 ,  A47B95/02

CPC classification number: H05K7/1411 ,  G06F1/181

Abstract: An assembly for facilitating the installation, securement and removal of a computer component from a computer chassis. The assembly includes a base connectable to the computer chassis and a handle pivotally connected to the base. The handle includes a notch and tab portion at each end for engaging a portion of the computer chassis for facilitating the installation of the component with the computer chassis when the handle is pivoted in a first direction and for facilitating the removal of the component from within the computer chassis when the handle is pivoted in a second direction. The handle further includes an aperture for receiving a flexible interlock tab connected to the base for releasable interlocking the handle and the base together, such that this, along with the tab portions of the handle, facilitate securing the computer component within the computer chassis.

Abstract translation: 用于便于从计算机机箱安装，固定和移除计算机组件的组件。 组件包括可连接到计算机机箱的基座和可枢转地连接到基座的手柄。 手柄在每个端部处包括凹口和突出部分，用于接合计算机机箱的一部分，以便当手柄沿第一方向枢转时便于将部件安装到计算机机架上，并且便于将部件从内部 当手柄沿第二方向枢转时，计算机机箱。 手柄还包括用于接收连接到基座的柔性互锁突出部的孔，用于将手柄和基座可释放地互锁在一起，使得这与手柄的突出部分一起有助于将计算机部件固定在计算机机箱内。

公开(公告)号：US5517646A

公开(公告)日：1996-05-14

申请号：US233032

申请日：1994-04-25

Applicant: Gary J. Piccirillo ,  Mark W. Welker ,  John S. Thayer

Inventor： Gary J. Piccirillo ,  Mark W. Welker ,  John S. Thayer

IPC: G06F13/40 ,  G06F13/00 ,  G06F9/00

CPC classification number: G06F13/4072

Abstract: A circuit for configuring a Plug and Play expansion card in one of three ways. The first is the standard Plug and Play configuration method, wherein expansion cards go through the isolation process to obtain unique Card Select Numbers (CSN). This method requires the existence of a dedicated serial EEPROM to store the system resource data for the expansion cards. However, when an expansion card is directly mounted onto a system board, it becomes a system board device. This allows the separate serial EEPROM to be removed. To implement, two alternative configuration modes are provided, wherein the expansion card can be configured under main CPU control. In these alternative modes, the configuration data is stored in the main system BIOS ROM. In the first mode, a register in the expansion card is mapped to a fixed ISA I/O address. In the second mode, the register is controlled by a dedicated pin, thus allowing it to be mapped to any ISA I/O address. To determine which configuration mode is used by the expansion card, pullup or pulldown resistors are connected to certain expansion card output pins. A second embodiment is also described wherein a static random access memory (SRAM) is utilized to store the serial identifier and the resource data. In this embodiment, the system BIOS initially writes the serial identifier and resource data into the SRAM. After this is done, a Plug and Play configuration process is invoked, in which the serial identifier is retrieved from the SRAM rather than the serial EEPROM.

Abstract translation: 用于以三种方式之一配置即插即用扩展卡的电路。 第一种是标准的即插即用配置方法，其中扩展卡通过隔离过程获得唯一的卡选择号码（CSN）。 该方法需要专用串行EEPROM来存储扩展卡的系统资源数据。 然而，当扩展卡直接安装在系统板上时，它成为系统板设备。 这允许单独的串行EEPROM被去除。 为了实现，提供了两种替代配置模式，其中扩展卡可以在主CPU控制下配置。 在这些替代模式下，配置数据存储在主系统BIOS ROM中。 在第一种模式下，扩展卡中的寄存器映射到固定的ISA I / O地址。 在第二种模式下，寄存器由专用引脚控制，从而允许寄存器映射到任何ISA I / O地址。 要确定扩展卡使用的配置模式，上拉或下拉电阻连接到某些扩展卡输出引脚。 还描述了其中使用静态随机存取存储器（SRAM）来存储串行标识符和资源数据的第二实施例。 在本实施例中，系统BIOS首先将串行标识符和资源数据写入SRAM。 完成之后，将调用即插即用配置过程，其中从SRAM而不是串行EEPROM检索串行标识符。

公开(公告)号：US5509139A

公开(公告)日：1996-04-16

申请号：US34300

申请日：1993-03-22

Applicant: Basem A. Ayash ,  Gary W. Thome

Inventor： Basem A. Ayash ,  Gary W. Thome

IPC: G06F9/46 ,  G06F9/48 ,  G06F12/02 ,  G06F12/06 ,  G06F13/24

CPC classification number: G06F9/4812 ,  G06F12/02 ,  G06F13/24 ,  G06F9/463

Abstract: A system management mode address correction system for a computer provides correct address values on the address bus when the computer is in system management mode. Conventionally, bit 20 of the microprocessor's address outputs may be masked by asserting the FORCE A20 signal. The computer system also operates in a system management mode, which requires all of the address bits to be available for proper access to the system management interrupt vector. When the computer is in system management mode, the computer's microprocessor asserts a system management interrupt active (SMIACT*) signal. This signal is provided to a circuit which also receives the FORCE A20 signal. While the SMIACT signal is deactivated, the control circuit provides the true FORCE A20 signal to the computer system. When an SMI occurs, the SMIACT signal is activated and the FORCE A20 signal is disabled. As a result, the address generated by the microprocessor is asserted on the address bus.

Abstract translation: 当计算机处于系统管理模式时，用于计算机的系统管理模式地址校正系统在地址总线上提供正确的地址值。 通常，微处理器地址输出的位20可以通过声明FORCE A20信号来屏蔽。 计算机系统还以系统管理模式操作，这要求所有地址位可用于正确访问系统管理中断向量。 当计算机处于系统管理模式时，计算机的微处理器断言系统管理中断激活（SMIACT *）信号。 该信号被提供给也接收FORCE A20信号的电路。 当SMIACT信号被禁用时，控制电路将真实的FORCE A20信号提供给计算机系统。 发生SMI时，SMIACT信号被激活，并且FORCE A20信号被禁止。 结果，微处理器产生的地址在地址总线上被断言。

公开(公告)号：US5507003A

公开(公告)日：1996-04-09

申请号：US338885

申请日：1994-11-14

Applicant: Jeff D. Pipkins

Inventor： Jeff D. Pipkins

IPC: G06F3/12 ,  G06F13/42 ,  G06F13/00

CPC classification number: G06F13/4269 ,  G06F13/4226 ,  G06F3/1293 ,  G06F3/1296

Abstract: A protocol provides bidirectional communication capability between a host computer and a printer over a parallel interface, the host computer and the printer having a forward channel therebetween for the transfer of signals from the host computer to the printer. The protocol includes conventions for turning the forward channel around so as to establish a reverse channel to allow transfer of data from the printer to the host computer, conventions for controlling the transfer of data from the printer to the host computer over the reverse channel, and conventions for turning the reverse channel back around so as to re-establish the forward channel.

Abstract translation: 协议通过并行接口在主计算机和打印机之间提供双向通信能力，主计算机和打印机之间具有前向信道，用于将信号从主计算机传送到打印机。 该协议包括用于转向前向信道的惯例，以便建立反向信道以允许数据从打印机传送到主计算机，用于控制通过反向信道从打印机传送到主计算机的数据的约定，以及 将反向通道反转的约定，以重新建立前进通道。

公开(公告)号：US5479087A

公开(公告)日：1995-12-26

申请号：US955693

申请日：1992-10-02

Applicant: Robert S. Wright

Inventor： Robert S. Wright

IPC: G05F1/14 ,  H02M3/335 ,  G05F1/577

CPC classification number: G05F1/14 ,  H02M3/33561

Abstract: A synchronized switch tapped coupled inductor circuit which couples a first closed-loop regulated output of a forward converter switching power supply to a second output to assist in regulating the voltage of the second output. The switched power supply includes a converter transformer which is implemented as a forward converter providing the multiple outputs. The second output includes a storage inductor which is coupled to a storage inductor of the first output. The second coupled inductor includes a center tap which is connected to a synchronized switch. The synchronized switch is further connected to the first output and coupled to the converter transformer to detect the forward and flyback portions of each cycle. During the flyback portion of each cycle, the switch is turned on coupling the center tap to the first output. During the forward portion of each cycle, the switch is turned off, isolating the outputs from each other.

Abstract translation: 同步开关抽头耦合电感器电路，其将正激变换器开关电源的第一闭环稳压输出耦合到第二输出端，以辅助调节第二输出的电压。 开关电源包括转换器变压器，其实现为提供多个输出的正向转换器。 第二输出包括耦合到第一输出的存储电感器的存储电感器。 第二耦合电感器包括连接到同步开关的中心抽头。 同步开关进一步连接到第一输出并耦合到转换器变压器以检测每个周期的正向和反向部分。 在每个循环的回扫部分期间，打开开关将中心抽头与第一输出相连。 在每个周期的前进部分，关闭开关，隔离输出。

公开(公告)号：US5473766A

公开(公告)日：1995-12-05

申请号：US298362

申请日：1994-08-30

Applicant: Charles N. Shaver

Inventor： Charles N. Shaver

IPC: G06F13/40 ,  G06F13/00

CPC classification number: G06F13/4068

Abstract: A switching circuit controls the routing of various signals of the computer system to and from the various pins of a microprocessor socket. A microprocessor rests in the socket and can be removed and replaced by another microprocessor. Variations in the pin arrangements of the two processors can be compensated for by appropriately setting the switches on the processor card. The use of 486SX, 487SX and 486DX microprocessors is illustrated in a single socket.

Abstract translation: 开关电路控制计算机系统的各种信号与微处理器插座的各个引脚的路由。 微处理器位于插座中，可以被另一个微处理器取下并更换。 可以通过适当地设置处理器卡上的开关来补偿两个处理器的引脚布置的变化。 使用486SX，487SX和486DX微处理器在单个插座中进行了说明。

公开(公告)号：US5469548A

公开(公告)日：1995-11-21

申请号：US263018

申请日：1994-06-20

Applicant: Ryan A. Callison ,  Gregory T. Chandler ,  Thomas W. Grieff

Inventor： Ryan A. Callison ,  Gregory T. Chandler ,  Thomas W. Grieff

IPC: G06F3/06 ,  G06F12/08 ,  G06F13/12 ,  G06F7/22

CPC classification number: G06F3/0601 ,  G06F12/0866 ,  G06F13/124 ,  G06F2003/0692

Abstract: A disk array controller board which utilizes an EISA bus master which is a slave on its internal data bus to allow an advanced drive array controller chip (ADAC) to operate as a master. The ADAC is connected to transfer buffer RAM. The protocol of the internal data bus provides for a cycle to load a host memory address into the bus slave, to provide transfer count information and slave specific information and for a series of data transfer cycles. The local processor is connected to the EISA bus master and the ADAC to control operations and to provide certain information. The ADAC is controlled by structures referred to as command descriptor blocks (CDBs). Each CDB includes information which describes the various addresses, control bits and functional bits used by the ADAC to perform its transfer operations. The local processor directly writes and deposits data forming a CDB into the transfer buffer RAM. The ADAC obtains the CDB, loads the data into registers and then performs operations according to the information contained in these registers until a transfer is done. The ADAC itself performs operations, including automatic stripe scattering and gathering to develop contiguous host memory fields from striped array data. A series of CDBs can be chained so that a complex series of tasks can be developed. In one variation a string of CDBs is developed to transfer data but some data is transferred to the bit bucket, while other data is actually transferred.

Abstract translation: 一种磁盘阵列控制器板，其使用作为其内部数据总线上的从机的EISA总线主机，以允许先进的驱动器阵列控制器芯片（ADAC）作为主机操作。 ADAC连接到传输缓冲RAM。 内部数据总线的协议提供了将主机存储器地址加载到总线从站中的周期，以提供传输计数信息和从属特定信息以及一系列数据传输周期。 本地处理器连接到EISA总线主控和ADAC控制操作并提供某些信息。 ADAC由称为命令描述符块（CDB）的结构控制。 每个CDB包括描述ADAC用于执行其传送操作的各种地址，控制位和功能位的信息。 本地处理器直接将形成CDB的数据写入并存储到传送缓冲器RAM中。 ADAC获得CDB，将数据加载到寄存器中，然后根据这些寄存器中包含的信息执行操作，直到传输完成。 ADAC本身执行操作，包括自动条纹散射和收集，以从条形阵列数据开发连续的主机内存字段。 一系列CDB可以链接，以便可以开发一系列复杂的任务。 在一个变化中，开发了一串CDB来传输数据，但是一些数据被传送到比特桶，而其他数据被实际传输。

公开(公告)号：US5469545A

公开(公告)日：1995-11-21

申请号：US335557

申请日：1994-11-07

Applicant: Michael R. Vanbuskirk ,  Jon M. Meinecke

Inventor： Michael R. Vanbuskirk ,  Jon M. Meinecke

IPC: G06F13/40 ,  G06F13/00

CPC classification number: G06F13/4022

Abstract: A communication system including one or more host adapters connected to a host computer, each adapter having multiple serial communication ports for transferring data between the computer and several TTY devices. Several of the adapter's serial ports include a high speed serial link for communicating with a data concentrator. The adapter automatically detects the presence of a concentrator connected to a switchable port and switches to the high speed link. Each concentrator includes multiple serial ports for communicating with TTY devices, and a high speed serial link for communicating with the adapter's high speed link. The concentrators allow more than one TTY device to share a single adapter serial port. Data from all of the TTY devices is accumulated into an adapter data buffer during a configurable time period or until a certain amount of data is accumulated, at which time the adapter interrupts the computer and transfers the accumulated data to the computer in one transfer operation. Likewise, the computer accumulates data for the TTY devices and transfers this data to the adapter in one transfer operation. Communication between the adapters and concentrators through the high speed serial communication link is implemented using a small fixed-size addressed packet to achieve a low overhead, high performance communications protocol. Each high speed link between an adapter and a concentrator is implemented to provide inherent flow control of data. The concentrators include a fail safe global flow control mechanism to prevent overflow of data from the TTY devices.

Abstract translation: 一种通信系统，包括连接到主计算机的一个或多个主机适配器，每个适配器具有用于在计算机和多个TTY设备之间传送数据的多个串行通信端口。 几个适配器的串行端口包括用于与数据集中器进行通信的高速串行链路。 适配器自动检测连接到可切换端口的集线器的存在并切换到高速链路。 每个集线器包括用于与TTY设备通信的多个串行端口，以及用于与适配器的高速链路通信的高速串行链路。 集线器允许多个TTY设备共享单个适配器串行端口。 来自所有TTY设备的数据在可配置的时间段期间累积到适配器数据缓冲器中，或者直到一定量的数据被累积为止，此时适配器中断计算机并在一次传送操作中将累积的数据传送到计算机。 同样，计算机累积TTY设备的数据，并在一次传输操作中将该数据传输到适配器。 通过高速串行通信链路，适配器和集线器之间的通信使用小的固定大小的寻址分组来实现，以实现低开销，高性能的通信协议。 实现适配器和集中器之间的每个高速链路以提供数据的固有流控制。 集中器包括一个故障安全的全局流量控制机制，以防止来自TTY设备的数据溢出。

公开(公告)号：US5463753A

公开(公告)日：1995-10-31

申请号：US955501

申请日：1992-10-02

Applicant: Walter G. Fry ,  Jeff W. Wolford

Inventor： Walter G. Fry ,  Jeff W. Wolford

IPC: G06F12/08 ,  G06F13/36 ,  G06F13/14

CPC classification number: G06F13/36 ,  G06F12/0831

Abstract: A method and apparatus which reduces the non-snoop window of a cache controller during certain operations to increase host bus efficiency. The cache controller requires a bus grant signal to perform cycles and cannot snoop cycles after the bus grant signal has been provided until the cycle completes. Cache interface logic monitors the cache controller for cycles that require either the expansion bus or the local I/O bus. When such a cycle is detected, the apparatus begins the cycle and does not assert the bus grant signal to the cache controller. The cache controller thus believes that the cycle has not yet begun and is thus able to perform other operations, such as snooping other host bus cycles. During this time, the cycle executes. When the read data is returned or when the write data reaches its destination, the interface logic provides the bus grant cycle to the cache controller at an appropriate time. By delaying the bus grant signal in this manner, the non-snoop window is reduced.

Abstract translation: 一种在某些操作期间减少高速缓存控制器的非窥探窗口以增加主机总线效率的方法和装置。 高速缓存控制器需要总线授权信号来执行周期，并且在提供总线授权信号直到循环完成之后才能窥探周期。 缓存接口逻辑监控缓存控制器的周期，这些周期需要扩展总线或本地I / O总线。 当检测到这样的周期时，设备开始周期，并且不向总线授权信号断言到高速缓存控制器。 因此，高速缓存控制器认为该周期尚未开始，因此能够执行其他操作，例如窥探其他主机总线周期。 在此期间，循环执行。 当读取数据返回或写数据到达其目的地时，接口逻辑在适当的时间向缓存控制器提供总线授权周期。 通过以这种方式延迟总线授权信号，减少非窥视窗口。