Abstract:
A power management system including a battery-powered application, in which an input current is supplied by a source of current that may be a current-constrained source, such as a USB port, to a battery for charging the battery and to an application load. Battery charging current is supplied to the battery for a period of time based on magnitude of battery charging current, so that charging current of lesser magnitude is applied to the battery for a greater period of time. In accord with one implementation, battery charging current is determined by monitoring the difference between a programmed charging current, dependent on battery type, and magnitude of current used by the load. Change of battery charging current due to voltage mode charging, when charge current begins to drop as the battery approaches full charge, is detected, and in response, the charging period is set to a fixed charging period based on the battery.
Abstract:
Transition delays in a level shift circuit are equalized by generating a first signal related to the state of the input signal, a second signal inversely related to the state of the input signal, and a third signal that is reciprocal to the second signal. Upon transition of the input signal from a high state to a low state, the third signal is selected for controlling the output until the first signal attains a high state. The first signal is selected for controlling the output when it has reached a high state after the input signal transition. The first signal remains selected upon transition of the input signal from a high state to a low state. Thus, output delays are equalized and reduced to the shortest delay.
Abstract:
A clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. The clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and supplies a second current in response. The first current is received by the first bipolar transistor, and the second current is received by the second bipolar transistor. The difference between the base-emitter junction voltages of the first and second bipolar transistors, in part, defines the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base/gate terminals of the transistors disposed in the current mirror. The circuit optionally includes a pair of cross-coupled transistors to reduce the output impedance and improve the power supply rejection ratio.
Abstract:
The present disclosure relates to simulating inductors wound on a ferromagnetic core as the magnetic material saturates. In one application, the present disclosure is advantageously used to model the asymmetric minor hysteresis loops commonly traversed by the output inductor of a switch mode power supply. An advantage of the subject matter of the disclosure is that it allows practical nonlinear inductors to be modeled in a computationally lightweight manner without conventional non-physical behavior under asymmetric minor hysteresis loop traversals. The disclosure is also conveniently applicable to practical ferromagnetic core materials because, in one particular implementation, the input parameters to the model are the core's coercive force (Hc), remnant magnetization flux density (Br), and saturation flux density (Bs).
Abstract:
A voltage regulator includes an input connectable to a voltage source and an output connectable to a load. The voltage regulator includes an inductor coupled to the output, a switch between the input and the inductor, and a current control loop configured to control the duty cycle of the switch to regulate voltage at the output, wherein the duty cycle being based on both a peak and valley threshold level of current flowing through the inductor.
Abstract:
Various concepts and techniques are disclosed for measuring the voltage of a power source. An apparatus includes a voltage metering circuit and a transformer having a first winding coupled to the voltage metering circuit and a second winding for coupling to a power source.
Abstract:
A spread spectrum frequency modulated oscillator circuit usable as a clock comprises a reference component such as a resistor, a voltage controlled oscillator and a first circuit coupled to the reference component and voltage controlled oscillator and configured to supply a first control signal to the oscillator to cause the oscillator to oscillate at a frequency corresponding to a value of the reference component. A second circuit configured to supply a random signal to the oscillator causes the frequency of the oscillator to dither. To cause the oscillator to exhibit random frequency modulation that is fast enough to reduce EMI but not too fast for controlled devices such as switching regulators to track, the oscillator includes a third circuit configured to control (1) a rate of change of the oscillator frequency such that the rate of change is a fixed percentage of the oscillator frequency, and (2) an amount of frequency change in the oscillator frequency such that the amount of frequency change is a fixed percentage of the oscillator frequency.
Abstract:
Digital to analog converter circuits and methods are provided for producing an analog output voltage indicative of a digital input signal with at least partial insensitivity to error gradients. Described are split-core resistive elements, which include a plurality of one-dimensional or multi-dimensional resistive strings, that may be used to reduce or substantially eliminate the effects that error gradients have on the linearity of the analog output voltages of a resistive string or interpolating amplifier DACs. The resistor strings that make up the split-core resistive elements are configured in such a manner that combining respective output voltages from each of the resistor strings results in an analog output voltage that is at least partially insensitive to the effects of error gradients.
Abstract:
A lead frame is configured for use with a singulation apparatus that eliminates flash. A die pad is attached to sides of the frame by tie bars and peripheral portions. The peripheral portions have cutout sections defining openings that are bridged by lead frame segments. The apparatus applies a downward force to the lead frame segments and translates the downward force to a horizontal force applied to the tie bars. The singulation process confines movement of the lead frame metal to within the plane of the lead frame.
Abstract:
A clock oscillator system for use in providing the switching regulator duty cycle control in a fixed frequency (no cycle skipping) operation is provided. In one embodiment, the circuit according to the invention uses an analog feedback loop to extend the switch ON time of the clock cycle by controlling the oscillator charging current and, thereby, increase the duty cycle. Preferably, this circuit can achieve very high switching duty cycle and/or very low switching duty cycle in a PWM switching regulator operated in very low drop-out operation when very high duty cycle is required or in other conditions when very low duty cycle is required.