Power management circuit and methodology for battery-powered systems
    91.
    发明授权
    Power management circuit and methodology for battery-powered systems 有权
    电池供电系统的电源管理电路和方法

    公开(公告)号:US07548041B2

    公开(公告)日:2009-06-16

    申请号:US11024473

    申请日:2004-12-30

    CPC classification number: H02J7/0068

    Abstract: A power management system including a battery-powered application, in which an input current is supplied by a source of current that may be a current-constrained source, such as a USB port, to a battery for charging the battery and to an application load. Battery charging current is supplied to the battery for a period of time based on magnitude of battery charging current, so that charging current of lesser magnitude is applied to the battery for a greater period of time. In accord with one implementation, battery charging current is determined by monitoring the difference between a programmed charging current, dependent on battery type, and magnitude of current used by the load. Change of battery charging current due to voltage mode charging, when charge current begins to drop as the battery approaches full charge, is detected, and in response, the charging period is set to a fixed charging period based on the battery.

    Abstract translation: 一种电源管理系统,包括电池供电的应用,其中输入电流由可能是电流受限的源(例如USB端口)的电流源提供给用于对电池充电的电池和应用负载 。 基于电池充电电流的大小,电池充电电流被提供给电池一段时间,使得较小的充电电流被更长时间地应用于电池。 根据一个实施方案,通过监视编程的充电电流(取决于电池类型)和负载所使用的电流的大小之间的差异来确定电池充电电流。 检测到当电池接近满充电时充电电流开始下降时由于电压模式充电而导致的电池充电电流的变化,作为响应,基于电池将充电期间设定为固定的充电期间。

    Level shift delay equalization circuit and methodology
    92.
    发明授权
    Level shift delay equalization circuit and methodology 有权
    电平移位延迟均衡电路和方法

    公开(公告)号:US07545173B2

    公开(公告)日:2009-06-09

    申请号:US11315146

    申请日:2005-12-23

    Applicant: Burt Lee Price

    Inventor: Burt Lee Price

    CPC classification number: H03K19/0013 H03K19/00323

    Abstract: Transition delays in a level shift circuit are equalized by generating a first signal related to the state of the input signal, a second signal inversely related to the state of the input signal, and a third signal that is reciprocal to the second signal. Upon transition of the input signal from a high state to a low state, the third signal is selected for controlling the output until the first signal attains a high state. The first signal is selected for controlling the output when it has reached a high state after the input signal transition. The first signal remains selected upon transition of the input signal from a high state to a low state. Thus, output delays are equalized and reduced to the shortest delay.

    Abstract translation: 通过产生与输入信号的状态相关的第一信号,与输入信号的状态相反的第二信号和与第二信号相反的第三信号,使电平移位电路中的转换延迟相等。 在将输入信号从高状态转换到低状态时,选择第三信号以控制输出,直到第一信号达到高状态。 选择第一个信号以在输入信号转换后达到高电平状态时控制输出。 当输入信号从高状态转变到低状态时,第一信号保持选择。 因此,输出延迟被均衡并且减小到最短的延迟。

    METHOD FOR CLAMPING A SEMICONDUCTOR REGION AT OR NEAR GROUND
    93.
    发明申请
    METHOD FOR CLAMPING A SEMICONDUCTOR REGION AT OR NEAR GROUND 审中-公开
    用于夹紧或接近半导体区域的方法

    公开(公告)号:US20090121770A1

    公开(公告)日:2009-05-14

    申请号:US12033600

    申请日:2008-02-19

    CPC classification number: G05F3/265 H01L27/0248

    Abstract: A clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. The clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and supplies a second current in response. The first current is received by the first bipolar transistor, and the second current is received by the second bipolar transistor. The difference between the base-emitter junction voltages of the first and second bipolar transistors, in part, defines the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base/gate terminals of the transistors disposed in the current mirror. The circuit optionally includes a pair of cross-coupled transistors to reduce the output impedance and improve the power supply rejection ratio.

    Abstract translation: 钳位电路钳位由n型半导体区域接收的电压,而不使用肖特基晶体管。 钳位电路包括电流镜以及第一和第二双极晶体管。 电流镜接收第一电流并提供响应的第二电流。 第一电流由第一双极晶体管接收,第二电流由第二双极晶体管接收。 第一和第二双极晶体管的基极 - 发射极结电压之间的差异部分地限定了n型区域被钳位的电压。 为了正确启动电路,从设置在电流反射镜中的晶体管的基极/栅极端子取出电流。 该电路可选地包括一对交叉耦合的晶体管,以减少输出阻抗并提高电源抑制比。

    Asymmetric minor hysteresis loop model and circuit simulator including the same
    94.
    发明授权
    Asymmetric minor hysteresis loop model and circuit simulator including the same 有权
    非对称小磁滞回线模型和电路模拟器包括相同

    公开(公告)号:US07502723B1

    公开(公告)日:2009-03-10

    申请号:US11216008

    申请日:2005-09-01

    CPC classification number: G06F17/5036

    Abstract: The present disclosure relates to simulating inductors wound on a ferromagnetic core as the magnetic material saturates. In one application, the present disclosure is advantageously used to model the asymmetric minor hysteresis loops commonly traversed by the output inductor of a switch mode power supply. An advantage of the subject matter of the disclosure is that it allows practical nonlinear inductors to be modeled in a computationally lightweight manner without conventional non-physical behavior under asymmetric minor hysteresis loop traversals. The disclosure is also conveniently applicable to practical ferromagnetic core materials because, in one particular implementation, the input parameters to the model are the core's coercive force (Hc), remnant magnetization flux density (Br), and saturation flux density (Bs).

    Abstract translation: 本公开涉及当磁性材料饱和时模拟缠绕在铁磁芯上的电感器。 在一个应用中,本公开有利地用于对通常由开关模式电源的输出电感器穿过的非对称次级磁滞回线进行建模。 本公开的主题的优点在于,其允许在非对称的小磁滞回线遍历下,以计算轻量级的方式对实际的非线性电感进行建模而无需常规的非物理行为。 本发明也适用于实际的铁磁芯材料,因为在一个具体实施方式中,模型的输入参数是核心的矫顽力(Hc),剩余磁通密度(Br)和饱和磁通密度(Bs)。

    Advanced current-mode control for switched regulators
    95.
    发明申请
    Advanced current-mode control for switched regulators 有权
    开关稳压器的高级电流模式控制

    公开(公告)号:US20080297122A1

    公开(公告)日:2008-12-04

    申请号:US11802960

    申请日:2007-05-29

    CPC classification number: H02M3/156 H02M3/1588 Y02B70/1466

    Abstract: A voltage regulator includes an input connectable to a voltage source and an output connectable to a load. The voltage regulator includes an inductor coupled to the output, a switch between the input and the inductor, and a current control loop configured to control the duty cycle of the switch to regulate voltage at the output, wherein the duty cycle being based on both a peak and valley threshold level of current flowing through the inductor.

    Abstract translation: 电压调节器包括可连接到电压源的输入端和可连接到负载的输出端。 电压调节器包括耦合到输出的电感器,在输入端和电感器之间的开关,以及电流控制回路,其被配置为控制开关的占空比以调节输出端的电压,其中占空比基于 峰值和谷值电流流经电感的电流。

    Method and apparatus for measuring the voltage of a power source
    96.
    发明申请
    Method and apparatus for measuring the voltage of a power source 有权
    用于测量电源电压的方法和装置

    公开(公告)号:US20080231257A1

    公开(公告)日:2008-09-25

    申请号:US11717126

    申请日:2007-03-13

    CPC classification number: G01R19/2506 G01R31/362 G01R31/3658 G01R31/40

    Abstract: Various concepts and techniques are disclosed for measuring the voltage of a power source. An apparatus includes a voltage metering circuit and a transformer having a first winding coupled to the voltage metering circuit and a second winding for coupling to a power source.

    Abstract translation: 公开了用于测量电源电压的各种概念和技术。 一种装置包括电压计量电路和具有耦合到电压计量电路的第一绕组和用于耦合到电源的第二绕组的变压器。

    Spread spectrum modulation of a clock signal for reduction of electromagnetic interference
    97.
    发明授权
    Spread spectrum modulation of a clock signal for reduction of electromagnetic interference 有权
    扩展时钟信号的频谱调制,以减少电磁干扰

    公开(公告)号:US07417509B2

    公开(公告)日:2008-08-26

    申请号:US11366590

    申请日:2006-03-03

    CPC classification number: H04B15/04

    Abstract: A spread spectrum frequency modulated oscillator circuit usable as a clock comprises a reference component such as a resistor, a voltage controlled oscillator and a first circuit coupled to the reference component and voltage controlled oscillator and configured to supply a first control signal to the oscillator to cause the oscillator to oscillate at a frequency corresponding to a value of the reference component. A second circuit configured to supply a random signal to the oscillator causes the frequency of the oscillator to dither. To cause the oscillator to exhibit random frequency modulation that is fast enough to reduce EMI but not too fast for controlled devices such as switching regulators to track, the oscillator includes a third circuit configured to control (1) a rate of change of the oscillator frequency such that the rate of change is a fixed percentage of the oscillator frequency, and (2) an amount of frequency change in the oscillator frequency such that the amount of frequency change is a fixed percentage of the oscillator frequency.

    Abstract translation: 可用作时钟的扩谱频率调制振荡器电路包括诸如电阻器,压控振荡器和耦合到参考部件和压控振荡器的第一电路的参考部件,并且被配置为向振荡器提供第一控制信号以引起 振荡器以对应于参考分量的值的频率振荡。 被配置为向振荡器提供随机信号的第二电路导致振荡器的频率抖动。 为了使振荡器呈现出足够快的随机频率调制以减少EMI,但对于诸如开关稳压器之间的受控设备来说不太快,振荡器包括被配置为控制(1)振荡器频率的变化率的第三电路 使得变化率是振荡器频率的固定百分比,和(2)振荡器频率的频率变化量,使得频率变化量是振荡器频率的固定百分比。

    Gradient insensitive split-core digital to analog converter
    98.
    发明授权
    Gradient insensitive split-core digital to analog converter 有权
    梯度不敏感的分裂芯数转换器

    公开(公告)号:US07414561B1

    公开(公告)日:2008-08-19

    申请号:US11704441

    申请日:2007-02-08

    CPC classification number: H03M1/0682 H03M1/682 H03M1/747 H03M1/765

    Abstract: Digital to analog converter circuits and methods are provided for producing an analog output voltage indicative of a digital input signal with at least partial insensitivity to error gradients. Described are split-core resistive elements, which include a plurality of one-dimensional or multi-dimensional resistive strings, that may be used to reduce or substantially eliminate the effects that error gradients have on the linearity of the analog output voltages of a resistive string or interpolating amplifier DACs. The resistor strings that make up the split-core resistive elements are configured in such a manner that combining respective output voltages from each of the resistor strings results in an analog output voltage that is at least partially insensitive to the effects of error gradients.

    Abstract translation: 提供数模转换器电路和方法用于产生表示对错误梯度至少部分不敏感的数字输入信号的模拟输出电压。 描述的是分离电阻元件,其包括多个一维或多维电阻串,其可用于减少或基本上消除误差梯度对电阻串的模拟输出电压的线性的影响 或内插放大器DAC。 构成分离电阻元件的电阻串以这样的方式配置,即组合来自每个电阻器串的各个输出电压导致对误差梯度的影响至少部分不敏感的模拟输出电压。

    Flashless lead frame with horizontal singulation
    99.
    发明授权
    Flashless lead frame with horizontal singulation 有权
    无闪烁引线框架,水平分割

    公开(公告)号:US07414302B2

    公开(公告)日:2008-08-19

    申请号:US11500359

    申请日:2006-08-08

    Applicant: David Pruitt

    Inventor: David Pruitt

    Abstract: A lead frame is configured for use with a singulation apparatus that eliminates flash. A die pad is attached to sides of the frame by tie bars and peripheral portions. The peripheral portions have cutout sections defining openings that are bridged by lead frame segments. The apparatus applies a downward force to the lead frame segments and translates the downward force to a horizontal force applied to the tie bars. The singulation process confines movement of the lead frame metal to within the plane of the lead frame.

    Abstract translation: 引线框架被配置为与消除闪光的单片设备一起使用。 模具垫通过连杆和周边部分附接到框架的侧面。 周边部分具有限定由引线框架段桥接的开口的切口部分。 该装置向引线框架段施加向下的力并将向下的力平移到施加到连接杆的水平力。 分割过程将引线框架金属的运动限制在引线框架的平面内。

    Switching regulator duty cycle control in a fixed frequency operation
    100.
    发明授权
    Switching regulator duty cycle control in a fixed frequency operation 有权
    在固定频率运行中切换调节器占空比控制

    公开(公告)号:US07388444B2

    公开(公告)日:2008-06-17

    申请号:US11242095

    申请日:2005-10-03

    Applicant: Chiawei Liao

    Inventor: Chiawei Liao

    CPC classification number: H03K7/08 H02M3/156

    Abstract: A clock oscillator system for use in providing the switching regulator duty cycle control in a fixed frequency (no cycle skipping) operation is provided. In one embodiment, the circuit according to the invention uses an analog feedback loop to extend the switch ON time of the clock cycle by controlling the oscillator charging current and, thereby, increase the duty cycle. Preferably, this circuit can achieve very high switching duty cycle and/or very low switching duty cycle in a PWM switching regulator operated in very low drop-out operation when very high duty cycle is required or in other conditions when very low duty cycle is required.

    Abstract translation: 提供了一种用于提供固定频率(无循环跳跃)操作的开关调节器占空比控制的时钟振荡器系统。 在一个实施例中,根据本发明的电路使用模拟反馈回路来通过控制振荡器充电电流来延长时钟周期的接通时间,从而增加占空比。 优选地,该电路可以实现非常高的开关占空比和/或非常低的开关占空比,该PWM开关调节器在非常低的占空比需要非常低的占空比时或在需要非常低的占空比时在其它条件下以极低的输出操作 。

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