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公开(公告)号：US11640795B2
公开(公告)日：2023-05-02
申请号：US17735260
申请日：2022-05-03
Inventor： Xuehuan Feng , Yongqian Li
IPC: G09G3/20 , G09G3/3266 , G11C19/28
Abstract: A shift register unit, a gate drive circuit, and a drive method are provided. The shift register unit includes a first input circuit, a second input circuit, and an output circuit. The first input circuit is configured to charge a first node in response to a first input signal to control a level of the first node; the second input circuit is configured to charge a second node in response to a second input signal to control a level of the second node; and the output circuit is configured to output an output signal to an output terminal under common control of the level of the first node and the level of the second node; the first input circuit includes a first transistor and a first capacitor, and a second electrode of the first capacitor is connected to the first electrode of the first transistor.
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92.发明授权公开(公告)号：US11594183B2
公开(公告)日：2023-02-28
申请号：US17264050
申请日：2020-06-12
Inventor： Xuehuan Feng , Yongqian Li
IPC: G09G3/32 , G09G3/3266 , G09G3/3225 , G11C19/28 , G09G3/36
Abstract: The present disclosure provides a shift resister unit, a gate driving circuit, a display device, and a method for controlling a shift register unit. The shift register unit incudes a first input sub-circuit, a first output sub-circuit, a first reset sub-circuit, a second input sub-circuit, and a third input sub-circuit. The first input sub-circuit is configured to change a potential of a first node in a first phase. The first output sub-circuit is configured to output a gate driving signal in the first phase and output a compensation driving signal in a second phase. The first reset sub-circuit is configured to reset the first node. The second input sub-circuit is configured to change a potential of a second node in the first phase and maintain the potential of the second node. The third input sub-circuit is configured to change the potential of the first node in the second phase.
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公开(公告)号：US11581372B2
公开(公告)日：2023-02-14
申请号：US16977510
申请日：2019-11-29
Inventor： Zhongyuan Wu , Yongqian Li , Can Yuan , Zhidong Yuan , Dacheng Zhang , Lang Liu
Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. At least one sub-pixel includes a storage capacitor. The storage capacitor includes a second capacitor electrode, a first capacitor electrode and a third capacitor electrode which are sequentially on the base substrate. The first capacitor electrode has a first capacitor electrode side and a second capacitor electrode side opposite to each other in the second direction, and the second capacitor electrode has a third capacitor electrode side and a fourth capacitor electrode side opposite to each other in the second direction; orthographic projections of the first capacitor electrode side and the second capacitor electrode side on the base substrate are between an orthographic projection of the third capacitor electrode side and an orthographic projection of the fourth capacitor electrode side on the base substrate.
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94.发明授权公开(公告)号：US11562677B2
公开(公告)日：2023-01-24
申请号：US17556652
申请日：2021-12-20
Inventor： Xuehuan Feng , Yongqian Li
Abstract: The present disclosure provides display apparatuses, gate drive circuits, shift register units and driving methods thereof. The shift register unit includes: an outputting module, configured to output a composite output signal under a control of a potential of a pull-up node; a pull-up module, configured to charge the pull-up node under a control of a display control signal terminal and charge the pull-up node under a control of a potential of a black insertion node; a first reset circuit configured to, under a control of the reset signal terminal and the potential of the black insertion node, control a voltage control node to communicate with the pull-up node; a current-limiting circuit, connected between the voltage control node and a first voltage terminal; and a charging module, configured to charge the voltage control node under the control of the potential of the pull-up node.
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公开(公告)号：US20220343861A1
公开(公告)日：2022-10-27
申请号：US17860347
申请日：2022-07-08
Inventor： Xuehuan Feng , Yongqian Li
IPC: G09G3/3266
Abstract: Disclosed is a shift register, a gate driving circuit, a display apparatus and a driving method, the shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a banking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of a first node, wherein the composite output signal includes a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.
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Patent Agency Ranking
96.发明授权公开(公告)号：US11482168B2
公开(公告)日：2022-10-25
申请号：US16956921
申请日：2019-08-08
Inventor： Xuehuan Feng , Yongqian Li
IPC: G09G3/3225 , G09G3/3266
Abstract: A gate driving unit, a circuit, a display substrate, a display panel, and a display device are provided. The gate driving unit includes an Nth stage of shift register unit and an (N+1)th stage of shift register unit, N is a positive integer. The Nth stage of shift register unit includes an Nth stage of pull-up node control circuit, and the (N+1)th stage of shift register unit includes an (N+1)th stage of pull-up node control circuit. The Nth stage of pull-up node control circuit is electrically connected to an Nth stage of pull-up node and a control line, respectively, is configured to control a potential of the Nth stage of pull-up node under the control of a control signal inputted by the control line. The (N+1)th stage of pull-up node control circuit is electrically connected to an (N+1)th stage of pull-up node and the control line, respectively, and is configured to control a potential of the (N+1)th stage of pull-up node under the control of the control signal inputted by the control line.
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公开(公告)号：US11476310B2
公开(公告)日：2022-10-18
申请号：US16977512
申请日：2019-11-29
Inventor： Zhongyuan Wu , Yongqian Li , Can Yuan , Meng Li , Zhidong Yuan , Dacheng Zhang , Lang Liu
Abstract: A display substrate and a display device are provided. The display substrate includes sub-pixels which are arranged in a sub-pixel array in a first direction and a second direction. At least one sub-pixel includes a first transistor, a second transistor, a third transistor, and a storage capacitor. An active layer of the third transistor includes a body region and a first via hole region successively arranged in the first direction and electrically connected with each other; a first electrode of the third transistor is electrically connected to the first via hole region through a first via hole which is shifted in the second direction with respect to the body region, allowing the active layer incudes a first active layer side connecting the body region and the first via hole region; an extension direction of the first active layer side intersects with both the first direction and the second direction.
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公开(公告)号：US11475824B2
公开(公告)日：2022-10-18
申请号：US16478366
申请日：2018-12-21
Inventor： Xuehuan Feng , Yongqian Li
IPC: G09G3/3266 , G09G3/20 , G11C19/28
Abstract: Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.
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公开(公告)号：US11469290B2
公开(公告)日：2022-10-11
申请号：US17040260
申请日：2019-11-29
Inventor： Zhongyuan Wu , Yongqian Li , Can Yuan , Meng Li , Zhidong Yuan , Xuehuan Feng , Lang Liu , Dacheng Zhang
Abstract: The present disclosure relates to the field of display technologies, and provides an array substrate, a manufacturing method thereof, and a display panel. In the array substrate, a substrate is provided with a first transistor and a second transistor, a first electrode of the first transistor is electrically connected to a gate of the second transistor; a conductive layer is disposed on the substrate, and includes a first conductor portion, a first semiconductor portion, a second conductor portion that are sequentially connected along a first direction; a first gate insulating layer is disposed on a side of the conductive layer away from the substrate; a first gate layer is disposed on a side of the first gate insulating layer away from the substrate to form the gate of the second transistor; a dielectric layer is disposed on the substrate to cover a part of the first conductor portion, a part of the second conductor portion and a part of the first gate layer, and an orthographic projection of a first via hole disposed on the dielectric layer on the substrate overlaps with orthographic projections of at least a part of the first conductor portion, at least a part of the second conductor portion and the first gate layer on the substrate; and a first source/drain layer is disposed on a side of the dielectric layer away from the substrate to cover the first via hole.
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公开(公告)号：US11455936B2
公开(公告)日：2022-09-27
申请号：US17294690
申请日：2020-08-20
Inventor： Xuehuan Feng , Yongqian Li
IPC: G09G5/00 , G09G3/20 , G11C19/28 , G09G3/3266
Abstract: A shift register and a drive method therefor, and a gate drive circuit. The shift register includes: an input sub-circuit, a detection control sub-circuit, an output sub-circuit, a first reset sub-circuit, and a pull-down sub-circuit. The detection control sub-circuit is respectively connected to a random detection signal end (OE), a signal input end (INPUT), a first clock signal end (CLKA), a first reset end (RST1), and a pull-up node (PU), and is configured to provide a signal of the first clock signal end (CLKA) for the pull-up node (PU) under the control of the signal input end (INPUT), the random detection signal end (OE), the first clock signal end (CLKA), and the first reset end (RST1).
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