公开(公告)号：US20180233210A1

公开(公告)日：2018-08-16

申请号：US15503830

申请日：2016-08-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Mingfu HAN ,  Guangliang SHANG ,  Yuanbo ZHANG ,  Yujie GAO ,  Yan YAN ,  Yingmeng MIAO ,  Seungwoo HAN ,  Zhihe JIN ,  Xing YAO ,  Haoliang ZHENG

IPC: G11C19/28 ,  G09G3/20

CPC classification number: G11C19/287 ,  G09G3/20 ,  G09G2300/0426 ,  G09G2310/0245 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/28

Abstract: A supplement resetting module for a gate driver circuit, including a pull-up control unit, a pull-down control unit, a clock signal input end, a predetermined level input end, a first control signal input end, a second control signal input end and a signal output end. A control end of the pull-up control unit is connected to the clock signal input end, an output end of the pull-up control unit is connected to the signal output end, a first control end of the pull-down control unit is connected to the first control signal input end, a second control end of the pull-down control unit is connected to the second control signal input end, an input end of the pull-down control unit is connected to the predetermined level input end, and an output end of the pull-down control unit is connected to the signal output end.

公开(公告)号：US20180188562A1

公开(公告)日：2018-07-05

申请号：US15794298

申请日：2017-10-26

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhihe JIN ,  Seungwoo HAN ,  Mingfu HAN ,  Xing YAO ,  Guangliang SHANG ,  Zhichong WANG ,  Lijun YUAN ,  Haoliang ZHENG ,  Yunsik IM

IPC: G02F1/1335 ,  G02F1/1343 ,  G02F1/133

CPC classification number: G02F1/1336 ,  G02F1/13306 ,  G02F1/133553 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/19 ,  G02F2001/133616 ,  G02F2001/133618 ,  G02F2201/12 ,  G02F2202/10 ,  G02F2202/101 ,  G02F2203/02

Abstract: The present application discloses a reflective display panel, a driving method thereof, a control method of a pixel unit and a reflective display device. The reflective display panel comprises: a base substrate, a reflective layer, first and second electrode layers, wherein the first electrode layer is on a side of the reflective layer distal to the base substrate, the second electrode layer is on a side of the first electrode layer distal to the base substrate and insulated from the first electrode layer, materials of the first and second electrode layers are each an electro-optic material, and orthogonal projections of the second and first electrode layers on the base substrate have overlapping areas corresponding to the pixel units.

公开(公告)号：US20180047329A1

公开(公告)日：2018-02-15

申请号：US15539220

申请日：2016-11-01

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang SHANG ,  Seungwoo HAN ,  Haoliang ZHENG ,  Xing YAO ,  Mingfu HAN ,  Hyunsic CHOI ,  Yunsik IM ,  Yinglong HUANG ,  Jungmok JUN ,  Xue DONG

IPC: G09G3/20 ,  G11C19/28

CPC classification number: G11C19/287 ,  G09G3/2096 ,  G09G3/36 ,  G09G3/3666 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2320/0223 ,  G11C5/063 ,  G11C19/28

Abstract: The present disclosure provides a shift register circuit, an array substrate, and a display device. For a first driver and a second driver adjacent to each other in a direction substantially perpendicular to the gate line, a first driving input wiring of the first driver is arranged to input a first clock driving signal to individual shift registers successively from a shift register at a first end position of the first driver to a shift register at a second end position of the first driver, and a second driving input wiring of the second driver is arranged to input a second clock driving signal to individual shift registers successively from a shift register at a second end position of the second driver to a shift register at a first end position of the second driver.