公开(公告)号：US10860766B1

公开(公告)日：2020-12-08

申请号：US16420881

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Mukund Sivaraman ,  Shail Aditya Gupta ,  Akella Sastry ,  Rishi Surendran ,  Philip B. James-Roxby ,  Samuel R. Bayliss ,  Vinod K. Kathail ,  Ajit K. Agarwal ,  Ralph D. Wittig

IPC: G06F30/347 ,  G06F8/41 ,  G06F16/901 ,  G06F30/394 ,  G06F12/1081 ,  G06F115/02

Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

公开(公告)号：US20200372200A1

公开(公告)日：2020-11-26

申请号：US16420881

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Mukund Sivaraman ,  Shail Aditya Gupta ,  Akella Sastry ,  Rishi Surendran ,  Philip B. James-Roxby ,  Samuel R. Bayliss ,  Vinod K. Kathail ,  Ajit K. Agarwal ,  Ralph D. Wittig

IPC: G06F30/347 ,  G06F8/41 ,  G06F16/901 ,  G06F12/1081 ,  G06F30/394

Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

公开(公告)号：US12159057B2

公开(公告)日：2024-12-03

申请号：US17934153

申请日：2022-09-21

Applicant: Xilinx, Inc.

Inventor： Chia-Jui Hsu ,  Mukund Sivaraman ,  Vinod K. Kathail

IPC: G06F3/06

Abstract: Implementing data flows of an application across a memory hierarchy of a data processing array includes receiving a data flow graph specifying an application for execution on the data processing array. A plurality of buffer objects corresponding to a plurality of different levels of the memory hierarchy of the data processing array and an external memory are identified. The plurality of buffer objects specify data flows. Buffer object parameters are determined. The buffer object parameters define properties of the data flows. Data that configures the data processing array to implement the data flows among the plurality of different levels of the memory hierarchy and the external memory is generated based on the plurality of buffer objects and the buffer object parameters.

公开(公告)号：US12135990B2

公开(公告)日：2024-11-05

申请号：US18091907

申请日：2022-12-30

Applicant: XILINX, INC.

Inventor： Chia-Jui Hsu ,  Mukund Sivaraman ,  Vinod Kathail

IPC: G06F9/48 ,  G06F8/41 ,  G06F9/54

Abstract: Modeling and compiling tensor processing applications using multi-layer adaptive data flow (ML-ADF) graphs, including folding the ML-ADF graph for temporal sharing of platform resources, computing schedules for runtime orchestration of kernel execution, memory reuse, tensor and sub-volume movement, and dataflow synchronization, and generating binary code for processors of the target computing platform and re-targetable controller code. The ML-ADF graph may represent: tensor processing of a layer of a neural network as data flow through the data nodes and distribution to compute tiles across memory hierarchy; data flow amongst layers of the neural network using connections amongst data nodes of the respective layers; and multi-dimension data partitioning and distribution using tiling parameters associated with ports of the data nodes.

公开(公告)号：US20240094944A1

公开(公告)日：2024-03-21

申请号：US17934153

申请日：2022-09-21

Applicant: Xilinx, Inc.

Inventor： Chia-Jui Hsu ,  Mukund Sivaraman ,  Vinod K. Kathail

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0622 ,  G06F3/0683

Abstract: Implementing data flows of an application across a memory hierarchy of a data processing array includes receiving a data flow graph specifying an application for execution on the data processing array. A plurality of buffer objects corresponding to a plurality of different levels of the memory hierarchy of the data processing array and an external memory are identified. The plurality of buffer objects specify data flows. Buffer object parameters are determined. The buffer object parameters define properties of the data flows. Data that configures the data processing array to implement the data flows among the plurality of different levels of the memory hierarchy and the external memory is generated based on the plurality of buffer objects and the buffer object parameters.