公开(公告)号：US20190123728A1

公开(公告)日：2019-04-25

申请号：US15788617

申请日：2017-10-19

Applicant: Xilinx, Inc.

Inventor： Hai Bing Zhao ,  Kee Hian Tan ,  Ping-Chuan Chiang ,  Yohan Frans

IPC: H03K5/156 ,  H04L7/033 ,  H04L7/00

Abstract: A quadrature clock correction (QCC) circuit includes: a first pair of clock correction circuits that output in-phase and anti-in-phase clock signals, respectively, of a four-phase clock signal; a second pair of clock correction circuits that output quadrature-phase and anti-quadrature-phase clock signals, respectively, of the four-phase clock signal; a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal; and a calibration circuit configured to supply a first pair of control signals to each the first pair of clock correction circuits, and a second pair of control signals to each of the second pair of clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit.

公开(公告)号：US10680592B2

公开(公告)日：2020-06-09

申请号：US15788617

申请日：2017-10-19

Applicant: Xilinx, Inc.

Inventor： Hai Bing Zhao ,  Kee Hian Tan ,  Ping-Chuan Chiang ,  Yohan Frans

IPC: H04L7/00 ,  H04L7/033 ,  H03K5/156

Abstract: A quadrature clock correction (QCC) circuit includes: a first pair of clock correction circuits that output in-phase and anti-in-phase clock signals, respectively, of a four-phase clock signal; a second pair of clock correction circuits that output quadrature-phase and anti-quadrature-phase clock signals, respectively, of the four-phase clock signal; a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal; and a calibration circuit configured to supply a first pair of control signals to each the first pair of clock correction circuits, and a second pair of control signals to each of the second pair of clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit.