公开(公告)号：US10749729B1

公开(公告)日：2020-08-18

申请号：US16424328

申请日：2019-05-28

Applicant: Xilinx, Inc.

Inventor： Alan C. Wong ,  Hong Sik Ahn ,  Edward Lee ,  Christopher J. Borrelli

IPC: H04L27/12 ,  H04B1/20 ,  H04L27/38 ,  H03G3/30 ,  H04B1/16 ,  H04L25/03

Abstract: A circuit includes an AGC adaptation circuit configured to receive a first signal generated based on an AGC output signal from an AGC circuit. The AGC circuit applies an AGC gain to an AGC input signal to generate the AGC output signal. The AGC adaptation circuit determines an observed value of the first signal, and determines a AGC adaptation step size based on the observed value and a predetermined target value associated with the first signal. The AGC adaptation circuit provides a second signal to adjust the AGC gain of the AGC circuit using the AGC adaptation step size.

公开(公告)号：US10812089B2

公开(公告)日：2020-10-20

申请号：US16357169

申请日：2019-03-18

Applicant: Xilinx, Inc.

Inventor： Caleb S. Leung ,  Edward Lee ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yohan Frans

IPC: H03L7/099 ,  H03K19/177 ,  H03L7/08

Abstract: Apparatus and associated methods relating to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and/or injection-locked oscillator (ILO) adaptation values during startup and loading the pre-calibrated values during rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each frequency of the plurality of frequency bands. A state machine may be coupled to the controllable frequency circuit and the data store configured to select a predetermined frequency band in response to a command signal, retrieve, from the data store, operational settings associated with the predetermined frequency band, and, apply the retrieved operational settings to the controllable frequency circuit. With the pre-calibration, PLL and/or ILO lock times during rate change in a multi-rate serializer/deserializer (SERDES) link may be advantageously reduced.

公开(公告)号：US20200304130A1

公开(公告)日：2020-09-24

申请号：US16357169

申请日：2019-03-18

Applicant: Xilinx, Inc.

Inventor： Caleb S. Leung ,  Edward Lee ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yohan Frans

IPC: H03L7/099 ,  H03L7/08 ,  H03K19/177

Abstract: Apparatus and associated methods relating to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and/or injection-locked oscillator (ILO) adaptation values during startup and loading the pre-calibrated values during rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each frequency of the plurality of frequency bands. A state machine may be coupled to the controllable frequency circuit and the data store configured to select a predetermined frequency band in response to a command signal, retrieve, from the data store, operational settings associated with the predetermined frequency band, and, apply the retrieved operational settings to the controllable frequency circuit. With the pre-calibration, PLL and/or ILO lock times during rate change in a multi-rate serializer/deserializer (SERDES) link may be advantageously reduced.