公开(公告)号：US09453870B1

公开(公告)日：2016-09-27

申请号：US14252958

申请日：2014-04-15

Applicant: Xilinx, Inc.

Inventor： Amitava Majumdar ,  Richard W. Swanson ,  Anna W. Wong ,  Suraj Ethirajan ,  Asim A. Bajwa ,  Jongheon Jeong

IPC: G01R31/14 ,  G01R31/02

CPC classification number: G01R31/021 ,  G01R19/2513 ,  G01R31/025 ,  G01R31/2853

Abstract: In an apparatus relating generally to an IC die, the IC die has a regulated power supply, a power supply grid, and a test circuit. The regulated power supply is biased between a source supply node and a source ground node, which are externally accessible nodes of the IC die. An internal supply node of the power supply grid is coupled to the regulated power supply. The test circuit is coupled to the internal supply node of the power supply grid. The test circuit is configured to test for at least one short in the power supply grid. The test circuit is configured to limit power through the power supply grid to less than that of a probe tip tolerance. The test circuit is configured to test for the at least one short in presence of background current leakage of the power supply grid.

Abstract translation: 在与IC芯片大致相关的装置中，IC芯片具有稳压电源，电源网格和测试电路。 稳压电源在源电源节点和源极接地节点之间偏置，源极接地节点是IC芯片的外部可访问节点。 电源网格的内部供电节点耦合到稳压电源。 测试电路耦合到电源网格的内部供电节点。 测试电路被配置为测试电源网格中的至少一个短路。 测试电路被配置为将电源网格的电力限制为小于探针尖端公差的电力。 测试电路被配置为在存在电源网格的背景电流泄漏的情况下测试至少一个短路。

公开(公告)号：US09559704B1

公开(公告)日：2017-01-31

申请号：US14938741

申请日：2015-11-11

Applicant: Xilinx, Inc.

Inventor： Anna W. Wong ,  Ankur Jain ,  Richard W. Swanson

IPC: H03L7/08 ,  H03L7/197

CPC classification number: H03L7/1974 ,  H03L7/18

Abstract: In an example, operating a PLL circuit includes generating an error signal in response to comparison of a reference clock signal having a reference frequency and a feedback clock signal having a feedback frequency, generating a plurality of clock signals having an output frequency based on the error signal, and generating the feedback clock signal from the plurality of clock signals based on a first divider value and a control value derived from a second divider value. Operating the PLL circuit further includes multiplying each of a first integer value and a first fractional value by a power of two to generate a second integer value and a second fractional value, respectively, generating the second divider value using a sigma-delta modulator (SDM) based on the second integer value and the second fractional value, and dividing the second divider value by the power of two to generate the first divider value.

Abstract translation: 在一个示例中，操作PLL电路包括响应于具有参考频率的参考时钟信号和具有反馈频率的反馈时钟信号的比较来产生误差信号，产生具有基于误差的输出频率的多个时钟信号 信号，并且基于第一分频器值和从第二分频值导出的控制值从多个时钟信号产生反馈时钟信号。 操作PLL电路还包括将第一整数值和第一分数值中的每一个乘以2的幂来分别产生第二整数值和第二分数值，以使用Σ-Δ调制器（SDM）产生第二分频器值 ），并且将第二分频值除以二的幂来产生第一分频值。