公开(公告)号：US10177794B1

公开(公告)日：2019-01-08

申请号：US15372221

申请日：2016-12-07

Applicant: Xilinx, Inc.

Inventor： Kumar Rahul ,  Amarnath Perla ,  Santosh Yachareni

IPC: G11C29/00 ,  H03M13/00 ,  G06F11/10 ,  G11C29/52 ,  H03M13/15

Abstract: An integrated circuit (IC) includes an encoder configured to receive input data including a plurality of data bits. The encoder includes a parity computation matrix circuit configured to arrange the data bits according to a matrix format to generate a parity computation matrix. A parity computation circuit is configured to compute a plurality of parity computation row terms corresponding to rows of the parity computation matrix respectively, compute a plurality of parity computation column terms corresponding to columns of the parity computation matrix respectively, and compute parity bits using the parity computation row terms and parity computation column terms. Write data including the data bits and the parity bits are provided to a write circuit. The write circuit writes the write data to a memory cell array in a memory.