公开(公告)号：US20250156585A1

公开(公告)日：2025-05-15

申请号：US18505173

申请日：2023-11-09

Applicant: Xilinx, Inc.

Inventor： Bin Dai Ochotta ,  Sudheendra Kusume ,  Alec J. Wong ,  Pradip K. Jha

IPC: G06F21/72 ,  G06F30/392 ,  G06F115/08 ,  H04L9/08 ,  H04L9/14

Abstract: A key block can be generated from a session key used by a computer-based design tool for a circuit design by encrypting the session key using computer hardware. The key block can be divided, by the computer hardware, into a plurality of sub-blocks. A plurality of enhanced sub-blocks can be generated by the computer hardware by encrypting each sub-block of the plurality of sub-blocks with a different key of a plurality of keys corresponding to a plurality of Intellectual Property (IP) cores of the circuit design. The plurality of enhanced sub-blocks can be stored in a memory.

公开(公告)号：US11281834B1

公开(公告)日：2022-03-22

申请号：US16531346

申请日：2019-08-05

Applicant: Xilinx, Inc.

Inventor： Rajvinder S. Klair ,  Alec J. Wong ,  Sahil Goyal ,  Amit Kasat ,  Brian Cotter ,  Herve Alexanian

IPC: G06F30/36 ,  G06F30/367 ,  G06F8/41 ,  G06F8/70 ,  G06F21/60 ,  G06F9/445 ,  G06F8/54

Abstract: Approaches for protection of HLL simulation models in a circuit design having unprotected high-level language (HLL) program code and first metadata of a shared library of executable simulation models that are based on sensitive HLL simulation models. A design tool determines a first storage location of the shared library based on the first metadata and compiles the unprotected HLL program code into an executable object. The design tool links the executable object with the library of executable simulation models from the first storage location and then simulates the circuit design by executing the executable object and loading the executable simulation models in response to initiation by the executable object.

公开(公告)号：US11232219B1

公开(公告)日：2022-01-25

申请号：US16264101

申请日：2019-01-31

Applicant: Xilinx, Inc.

Inventor： Bin Ochotta ,  Alec J. Wong ,  Nghia Do ,  Dennis McCrohan ,  David A. Knol ,  Premduth Vidyanandan ,  Satyam Jani

IPC: G06F21/62 ,  H04L9/08 ,  G06F21/10 ,  G06F21/76 ,  H04L9/32 ,  G06F21/60 ,  H04L9/14 ,  G06F21/64 ,  G06F21/12

Abstract: Removing protections on a session-key protected design include receiving a double encrypted vendor private key and an encrypted session key. The double encrypted vendor private key is decrypted into a single encrypted vendor-private key using a user private key, and the single encrypted vendor-private key is decrypted into a vendor private key using a vendor pass phrase. The encrypted session key is decrypted into a session key using the vendor private key, and the session-key protected design is decrypted into a plain design using the session key.

公开(公告)号：US10013517B1

公开(公告)日：2018-07-03

申请号：US14989683

申请日：2016-01-06

Applicant: Xilinx, Inc.

Inventor： Sheng Zhou ,  Bin Ochotta ,  Alec J. Wong ,  Pradip K. Jha ,  Qin Zhang

IPC: G06F17/00 ,  G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/66

Abstract: High level synthesis for a circuit design may include detecting, using a processor, an encrypted, high level programming language (HLL) core for inclusion in a circuit design, decrypting, using the processor, the encrypted HLL core into volatile memory, and generating, using the processor, an encrypted, intermediate representation (IR) of the circuit design including an encrypted IR of the HLL core. An encrypted hardware description language (HDL) circuit design may be generated, using the processor, from the encrypted IR of the circuit design. The encrypted HDL circuit design includes an encrypted HDL core that is functionally equivalent to the encrypted HLL core.

公开(公告)号：US09824170B1

公开(公告)日：2017-11-21

申请号：US14989676

申请日：2016-01-06

Applicant: Xilinx, Inc.

Inventor： Alec J. Wong ,  Pradip K. Jha ,  Steven Banks ,  Sudipto Chakraborty ,  Dennis McCrohan

IPC: G06F17/00 ,  G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5068

Abstract: Message filtering may include, during a first processing phase of a design specified in source code, creating a filter table including message filters and storing the filter table in a memory using a processor. Each message filter may specify a message criterion and an object identifier of the design. During a subsequent processing phase of the design, received messages may be compared with the message filters of the filter table using the processor. Responsive to determining that a selected message matches a message criterion and an object identifier of a selected message filter, the message may be suppressed using the processor.