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公开(公告)号：US12235950B2
公开(公告)日：2025-02-25
申请号：US17578292
申请日：2022-01-18
Applicant: XILINX, INC.
Inventor： Jaideep Dastidar , James Murray , Stefano Stabellini
Abstract: Embodiments herein describe partitioning hardware and software in a system on a chip (SoC) into a hierarchy. In one embodiment, the hierarchy includes three levels of hardware-software configurations, enabling security and/or safety isolation across those three levels. The levels can cover the processor subsystem with compute, memory, acceleration, and peripheral resources shared or divided across those three levels.
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