公开(公告)号：US20230145694A1

公开(公告)日：2023-05-11

申请号：US17837724

申请日：2022-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Wu ,  Ru-Shang Hsiao ,  I-Shan Huang ,  Ying Hsin Lu ,  C.J. Wu

IPC: H01L21/3065 ,  H01L21/311

CPC classification number: H01L21/3065 ,  H01L21/31138

Abstract: Analog and logic devices may coexist on a common integrated circuit chip, accommodating features with different pitches, linewidths, and pattern densities. Such differences in design and layout at various layers during manufacturing can cause process loading by contributing different amounts of reactants to surface chemical reactions. Such variation in the balance of chemical reactants can result in disparities in film thicknesses within the chip that can affect device performance. Embodiments of the present disclosure disclose a masking sequence that can alleviate process loading disparities during an undercut etch process adjacent to polysilicon structures.