公开(公告)号：US20250014943A1

公开(公告)日：2025-01-09

申请号：US18219259

申请日：2023-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zheng Yong LIANG ,  Wei-Ting YEH ,  I-Han HUANG ,  Chen-Hao WU ,  An-Hsuan LEE ,  Huang-Lin CHAO ,  Yu-Yun PENG ,  Keng-Chu LIN

IPC: H01L21/768 ,  H01L21/3105 ,  H01L23/00 ,  H01L29/66

Abstract: An integrated circuit (IC) chip with polish stop layers and a method of fabricating the IC chip are disclosed. The method includes forming a first IC chip having a device region and a peripheral region. Forming the first IC chip includes forming a device layer on a substrate, forming an interconnect structure on the device layer, depositing a first dielectric layer on a first portion of the interconnect structure in the peripheral region, depositing a second dielectric layer on the first dielectric layer and on a second portion of the interconnect structure in the device region, and performing a polishing process on the second dielectric layer to substantially coplanarize a top surface of the second dielectric layer with a top surface of the first dielectric layer. The method further includes performing a bonding process on the second dielectric layer to bond a second IC chip to the first IC chip.