公开(公告)号：US11087059B2

公开(公告)日：2021-08-10

申请号：US16906001

申请日：2020-06-19

Applicant: Synopsys, Inc.

Inventor： Anshu Malani ,  Paras Mal Jain ,  Sudeep Mondal

IPC: G06F30/33 ,  G06F30/327 ,  G06F119/12

Abstract: Techniques for verification of integrated circuit design are disclosed. A design relating to an integrated circuit is received (102). The design includes a first parameterized element and a second parameterized element (104). The first parameterized element is identified as a do-not-care (DNC) element based on usage of the first parameterized element in the design (106). A plurality of models relating to the design are generated by a processing device (110). A first value of the first parameterized element is not varied during the generating, based on the identification of the first parameterized element as a DNC element (108). A second value of the second parameterized element is varied during the generating (108).

公开(公告)号：US20160342727A1

公开(公告)日：2016-11-24

申请号：US14716422

申请日：2015-05-19

Applicant: Synopsys, Inc.

Inventor： Mohamed Shaker Sarwary ,  Paras Mal Jain ,  Anshu Malani

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F2217/84

Abstract: In a method of checking an integrated circuit design prior to running a simulation, a shoot-through RTL Checker reads RTL design files, uses a simulator delta cycle definitions to compute clock delta delays, and helps to correct and report any conditions that are expected will cause the simulation to generate incorrect results, in particular shoot-through conditions at circuit memory elements such as source and destination flip-flops or registers.

Abstract translation: 在运行仿真之前检查集成电路设计的方法中，直通RTL​​检查器读取RTL设计文件，使用模拟器增量循环定义来计算时钟延迟延迟，并帮助纠正和报告任何预期的条件 导致模拟产生不正确的结果，特别是在诸如源和目标触发器或寄存器的电路存储器元件的直通条件。