公开(公告)号：US20240040770A1

公开(公告)日：2024-02-01

申请号：US18194642

申请日：2023-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jina Kim ,  Kang-Uk Kim ,  Ho-In Ryu ,  Yunho Song ,  Dalhyeon Lee

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/482 ,  H10B12/485

Abstract: A memory device includes a substrate having first and second active patterns adjacent to each other and separated by a trench, the first and second active patterns including a first source/drain region; the second active pattern includes a second source/drain region. The second source/drain region includes first and second sidewall surfaces adjacent the first source/drain region and a connecting surface that connects the first and second sidewall surfaces. The second sidewall surface is set back from the first sidewall surface. An isolation layer is included in the trench and on the first sidewall surface. A bit line includes a contact part connected to the first source/drain region. A contact is coupled to the second source/drain region with a lower spacer between the contact and the contact part of the bit line, a landing pad on the contact, and a data storage element on the landing pad.