公开(公告)号：US20220020682A1

公开(公告)日：2022-01-20

申请号：US17163869

申请日：2021-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woonki LEE ,  Minsic KIM ,  Seunghun OH ,  Jinhyeong KIM ,  Junyeong AN ,  Jooyeon LEE ,  Sangwoo PYO

IPC: H01L23/528 ,  H01L23/60 ,  H01L23/522 ,  H01L23/00

Abstract: A semiconductor device includes bumps and a plurality of input/output areas on a substrate. Each of the input/output areas include semiconductor elements on the substrate, lower wiring patterns connected to the semiconductor elements, and input/output pins above and connected to the lower wiring patterns. The semiconductor elements provide a logic circuit and a protection circuit. The bumps are above the lower wiring patterns and connected to the input/output pins by upper wiring patterns. The input/output areas include a first input/output area and a second input/output area. The input/output areas includes a first circuit area including the electrostatic discharge protection circuit and a second circuit area including the logic circuit. In the first input/output area, the input/output pin is in the first circuit area. In the second input/output area, the input/output pin is in the second circuit area.

公开(公告)号：US20210287965A1

公开(公告)日：2021-09-16

申请号：US17104124

申请日：2020-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woonki LEE ,  Daehyung MYUNG ,  Yunho CHOI ,  Minsic KIM ,  Seunghun OH ,  Jinhyeong KIM ,  Junyeong AN ,  Jooyeon LEE ,  Sangwoo PYO

IPC: H01L23/49 ,  H01L23/00 ,  H01L27/02

Abstract: A semiconductor device includes a substrate, input/output areas in a first direction and a second direction, parallel to an upper surface of the substrate and intersecting to each other, the input/output areas each including semiconductor elements providing an input/output circuit, lower wiring patterns connected to the semiconductor elements, and input/output pins connected to the lower wiring patterns, and bumps connected to the input/output pins by upper wiring patterns on the same layer as the input/output pins. The input/output areas include a first input/output area and a second input/output area, and each of the first input/output area and the second input/output area includes a first area and a second area sequentially in the first direction, and in the first input/output area, the input/output pin is in the first area, and in the second input/output area, the input/output pin is in the second area.