公开(公告)号：US20220141054A1

公开(公告)日：2022-05-05

申请号：US17392742

申请日：2021-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihwan SEONG ,  Hyoungjoong KIM ,  Woongki MIN

IPC: H04L25/03

Abstract: A decision feedback equalizer including: a first input latch configured to generate a first output signal from first data received by the first input latch, wherein the first input latch includes: a first sub-circuit configured to receive the first data and a reference voltage, compare the first data and the reference voltage, and generate first internal signals having different transition timings according to a result of the comparison between the first data and the reference voltage; and a second sub-circuit configured to receive, as first feedback, a second output signal, which corresponds to second data received by the first latch earlier than the first data, and generate the first output signal, which compensates for a difference between the transition timings of the first internal signals, based on the first feedback.

公开(公告)号：US20230254186A1

公开(公告)日：2023-08-10

申请号：US18136967

申请日：2023-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Kihwan SEONG ,  Hyoungjoong KIM ,  Woongki MIN

IPC: H04L25/03

CPC classification number: H04L25/03019 ,  H04L25/03267 ,  H04B3/04

Abstract: A decision feedback equalizer including: a first input latch configured to generate a first output signal from first data received by the first input latch, wherein the first input latch includes: a first sub-circuit configured to receive the first data and a reference voltage, compare the first data and the reference voltage, and generate first internal signals having different transition timings according to a result of the comparison between the first data and the reference voltage; and a second sub-circuit configured to receive, as first feedback, a second output signal, which corresponds to second data received by the first latch earlier than the first data, and generate the first output signal, which compensates for a difference between the transition timings of the first internal signals, based on the first feedback.

公开(公告)号：US20240310414A1

公开(公告)日：2024-09-19

申请号：US18599336

申请日：2024-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woongki MIN ,  Hyeonji HAN ,  Myeongcheol KIM ,  Hyoungjoong KIM ,  Sangho KIM ,  Younggyun OH ,  Soomin LEE

IPC: G01R13/02

CPC classification number: G01R13/02

Abstract: An eye margin test method includes receiving an analog input signal, receiving an analog input signal, generating a recovery clock signal based on the digital input signal, delaying the recovery clock signal by adjusting a first delay control code, obtaining a first delay margin code based on the delayed recovery clock signal, delaying the digital input signal by adjusting a second delay control code, obtaining a second delay margin code based on the delayed digital input signal, and obtaining an eye margin code by adding the first delay margin code and the second delay margin code.

公开(公告)号：US20210211266A1

公开(公告)日：2021-07-08

申请号：US16990068

申请日：2020-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woongki MIN

IPC: H04L7/00 ,  H04L7/033

Abstract: An electronic device includes processing circuitry outputting first to third signals, delaying first to third signals to output fourth to sixth signals, generating a pulse signal based on the fourth signal, the fifth signal, and the sixth signal, detecting lengths of intervals, and adjusting at least one of a first code, a second code, and a third code based on fourth codes.