公开(公告)号：US10282325B2

公开(公告)日：2019-05-07

申请号：US15390888

申请日：2016-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suengchul Ryu ,  Je-Hyuck Song ,  Hyejeong Hong ,  Bumseok Yu

IPC: G06F13/36 ,  G06F13/38 ,  G06F13/40 ,  G06F13/00 ,  G06F13/18 ,  G06F13/16

Abstract: A semiconductor device includes a plurality of circuits, a general bus configured to be connected to each of the plurality of circuits and to provide a general channel among the plurality of circuits, and a designated bus configured to be connected to a subgroup of circuits from among the plurality of circuits and to provide a designated channel among the subgroup of circuits.

公开(公告)号：US12147356B2

公开(公告)日：2024-11-19

申请号：US17448971

申请日：2021-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suengchul Ryu

IPC: G06F13/12 ,  G06F13/16

Abstract: A storage device includes a memory device and a controller. The controller includes a programmable logic device which is reconfigurable, based on requests which are received from an outside of the storage device, to adaptively support a plurality of protocols depending on the requests. As the programmable logic device is programmed to support a first protocol among the plurality of protocols based on a first request which is received from the outside of the storage device with regard to the first protocol, the programmable logic device processes the first request in compliance with the first protocol, and the controller communicates with the memory device based on the first request such that the memory device stores or outputs data corresponding to the first request.

公开(公告)号：US11681553B2

公开(公告)日：2023-06-20

申请号：US16562623

申请日：2019-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hanmin Cho ,  Suengchul Ryu ,  Junghyun Hong

IPC: G06F12/02 ,  G06F9/50 ,  G06F13/16 ,  G06N3/06

CPC classification number: G06F9/5016 ,  G06F9/5027 ,  G06F12/0207 ,  G06F13/1673 ,  G06N3/06 ,  G06F2212/657 ,  G06F2212/7201

Abstract: A storage device includes an accelerator including a first processor, and a storage controller that uses a buffer memory as a working memory and includes a second processor different in type from the first processor. The second processor is configured to establish a first communication path between the first processor and the buffer memory responsive to a request of the first processor, and the first processor is configured to access the buffer memory through the first communication path.

公开(公告)号：US11132309B2

公开(公告)日：2021-09-28

申请号：US16510050

申请日：2019-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suengchul Ryu

IPC: G06F13/12 ,  G06F13/16

Abstract: A storage device includes a memory device and a controller. The controller includes a programmable logic device which is reconfigurable, based on requests which are received from an outside of the storage device, to adaptively support a plurality of protocols depending on the requests. As the programmable logic device is programmed to support a first protocol among the plurality of protocols based on a first request which is received from the outside of the storage device with regard to the first protocol, the programmable logic device processes the first request in compliance with the first protocol, and the controller communicates with the memory device based on the first request such that the memory device stores or outputs data corresponding to the first request.