公开(公告)号：US20200144245A1

公开(公告)日：2020-05-07

申请号：US16238009

申请日：2019-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sajal MITTAL ,  Abhishek GHOSH ,  Utkarsh GARG

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/118 ,  H03K19/0185

Abstract: Example embodiments provides a full adder integrated circuit (ADDF) for improving area and power of an integrated circuit (IC). The method includes receiving three input signals and generating three corresponding complementary output signals. Further, the method includes generating an internal signal using two complementary output signals out of the generated three corresponding complementary output signals, and one of the three input signals. Further, the method includes generating an output summation signal using a complementary output signal out of the generated three corresponding complementary output signals, the generated internal signal and a complementary internal signal of the generated internal signal. Further, the method includes generating a carry-out signal using two complementary output signal out of the generated three corresponding complementary output signals, the generated internal signal and the complementary internal signal. Example embodiments herein also provide a four input multiplexer Integrated circuit (MXT4) for reducing the area of the IC.

公开(公告)号：US20200266185A1

公开(公告)日：2020-08-20

申请号：US16865542

申请日：2020-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sajal MITTAL ,  Abhishek GHOSH ,  Utkarsh GARG

IPC: H01L27/02 ,  G06F30/392 ,  H03K19/0185

Abstract: Example embodiments provide a four input multiplexer integrated circuit (MXT4) associated with an integrated circuit (IC) and a method for reducing area and power of an integrated circuit (IC) using a MXT4, the MXT4 including a complementary signal generator circuit configured to receive first and second selection signals and to generate first and second complementary selection signals based on respective ones of the first and the second selection signals; and a p-type metal oxide semiconductor (PMOS) and an n-type metal oxide semiconductor (NMOS) stack switch circuit configured to transmit at least one input signal to an output based on the first and the second selection signals and the first and the second complementary selection signals.