公开(公告)号：US20180342462A1

公开(公告)日：2018-11-29

申请号：US15815083

申请日：2017-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Subhash KUCHANURI ,  Sidharth RASTOGI ,  Ranjan RAJEEV ,  Chul-hong PARK ,  Jae-seok YANG

IPC: H01L23/544 ,  H01L23/485 ,  G06F17/50 ,  H03K19/173

Abstract: An integrated circuit device includes: a pair of reference conductive lines arranged in parallel in a first direction in a first version logic cell and a pair of swap conductive lines arranged in parallel in a second version logic cell, wherein one reference conductive line and one swap conductive line in different wiring tracks of the pair of reference conductive lines and the pair of swap conductive lines have the same planar shape and the same length, and extend to intersect a cell boundary between the first version logic cell and the second version logic cell.