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    AUTOMATIC DELETION IN A PERSISTENT STORAGE DEVICE
    2.
    发明公开
    AUTOMATIC DELETION IN A PERSISTENT STORAGE DEVICE 审中-公开

    公开(公告)号：US20230195351A1

    公开(公告)日：2023-06-22

    申请号：US17583022

    申请日：2022-01-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ramdas P. KACHARE ,  Dongwan ZHAO

    IPC: G06F3/06

    CPC classification number: G06F3/0652 ,  G06F3/0608 ,  G06F3/0679

    Abstract: A system and method for automatic deletion in a persistent storage device. In some embodiments, the method includes: receiving, by a persistent storage device, a first read command, for a first logical block of data; determining that a total number of read operations, for the first logical block of data, equals or exceeds a first threshold value; and in response to determining that the total number of read operations, for the first logical block of data, equals or exceeds the first threshold value, arranging for deletion of the first logical block of data from the persistent storage device.

    SYSTEMS, METHODS, AND DEVICES FOR DATA STORAGE WITH SPECIFIED DATA TRANSFER RATE
    3.
    发明申请
    SYSTEMS, METHODS, AND DEVICES FOR DATA STORAGE WITH SPECIFIED DATA TRANSFER RATE 有权

    公开(公告)号：US20220291843A1

    公开(公告)日：2022-09-15

    申请号：US17308991

    申请日：2021-05-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ramdas P. KACHARE ,  Sungwook RYU

    IPC: G06F3/06

    Abstract: A method may include receiving, at a storage device, a command for a data transfer between the storage device and a host, determining a specified data rate for the data transfer, and performing the data transfer between the storage device and the host based on the command, wherein the storage device may control the data transfer based on the specified data rate. The data transfer may include a peak portion and an idle portion. The method may further include controlling, at the storage device, a peak portion and an idle portion of the data transfer based on the specified data rate. The method may further include controlling, at the storage device, the data transfer based on a peak burst size. The specified data rate may be received from the host and/or determined by the storage device by monitoring one or more parameters of a data transfer.

    METHODS AND APPARATUS FOR PEER-TO-PEER DATA CHANNELS FOR STORAGE DEVICES
    4.
    发明申请
    METHODS AND APPARATUS FOR PEER-TO-PEER DATA CHANNELS FOR STORAGE DEVICES 有权

    公开(公告)号：US20220255991A1

    公开(公告)日：2022-08-11

    申请号：US17728969

    申请日：2022-04-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ramdas P. KACHARE ,  Sompong Paul OLARIG ,  Matthew Shaun BRYSON

    IPC: H04L67/1042 ,  H04L41/0813 ,  H04L45/02 ,  H04L67/104 ,  G06F3/06 ,  H04L47/10 ,  G06F13/40 ,  H04L67/1097

    Abstract: A method may include transferring data between a host and a first storage device through a first storage interface, transferring data between the host and a second storage device through a second storage interface, and transferring data between the first storage device and the second storage device through a peer-to-peer channel. A storage system may include a host interface, a first storage device having a first storage interface coupled to the host interface, a second storage device having a second storage interface coupled to the host interface, and a peer-to-peer bus coupled between the first and second storage devices. A storage device may include a storage medium, a storage device controller coupled to the storage medium, a storage interface coupled to the storage device controller, and a peer-to-peer interface coupled to the storage device controller.

    SYSTEMS AND METHODS FOR DATA TRANSFER FOR COMPUTATIONAL STORAGE DEVICES
    5.
    发明申请
    SYSTEMS AND METHODS FOR DATA TRANSFER FOR COMPUTATIONAL STORAGE DEVICES 有权

    公开(公告)号：US20220236902A1

    公开(公告)日：2022-07-28

    申请号：US17495810

    申请日：2021-10-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Oscar P. PINTO ,  Ramdas P. KACHARE

    IPC: G06F3/06 ,  G06F9/54

    Abstract: Provided are systems, methods, and apparatuses for managing memory. The method can include: establishing a connection via an interface, between a host device and a storage device; and transferring data, via the interface, between first memory associated with the host device and second memory associated with the storage device by performing a data operation on the second memory by an application executed by the host, where the storage device includes a processing element that accelerates the data operation by performing at least one offload function on the data operation.

    STORAGE DEVICE-ASSISTED LIVE VIRTUAL MACHINE MIGRATION
    6.
    发明申请
    STORAGE DEVICE-ASSISTED LIVE VIRTUAL MACHINE MIGRATION 有权

    公开(公告)号：US20210263762A1

    公开(公告)日：2021-08-26

    申请号：US17006773

    申请日：2020-08-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ramdas P. KACHARE ,  Oscar P. PINTO ,  Yang seok KI

    IPC: G06F9/455 ,  G06F3/06 ,  G06F12/0862

    Abstract: A storage device is disclosed. The storage device may include at least one controller for a virtual machine (VM) that is on a source host. Storage in the storage device may store data for the VM. A second storage may store a storage state for the VM. A storage device controller may process at least one read request received from the controller for the VM using the first storage and at least one write request received from the controller for the VM using the first storage. A VM migration state monitor and capture module may assist in the migration of the VM from the source host to a destination host.

    NOVEL SSD ARCHITECTURE FOR FPGA BASED ACCELERATION
    7.
    发明申请
    NOVEL SSD ARCHITECTURE FOR FPGA BASED ACCELERATION 审中-公开

    公开(公告)号：US20190272242A1

    公开(公告)日：2019-09-05

    申请号：US16124183

    申请日：2018-09-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ramdas P. KACHARE ,  Fred WORLEY

    IPC: G06F13/16 ,  G06F13/42

    Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream port enables communication with the processor; a downstream port enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. A downstream filter associated with the downstream port may intercept an acceleration instruction associated with a downstream Filter Address Range (FAR) received from the storage device and deliver the acceleration instruction to the APM-F, the acceleration instruction being. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.

    NOVEL SSD ARCHITECTURE FOR FPGA BASED ACCELERATION
    8.
    发明申请
    NOVEL SSD ARCHITECTURE FOR FPGA BASED ACCELERATION 审中-公开

    公开(公告)号：US20190272240A1

    公开(公告)日：2019-09-05

    申请号：US16122865

    申请日：2018-09-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ramdas P. KACHARE ,  Fred WORLEY ,  Harry ROGERS ,  Wentao WU ,  Nagarajan SUBRAMANIYAN

    IPC: G06F13/16 ,  G06F13/42 ,  G06F13/40

    Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream interface enables communication with the processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.

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