公开(公告)号：US12120876B2

公开(公告)日：2024-10-15

申请号：US17679268

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon Baek ,  Miram Kwon ,  Seongjun Seo ,  Younghwan Son

IPC: H10B43/27 ,  H01L27/06 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L27/0688 ,  H10B43/40

Abstract: A semiconductor device includes a first substrate, circuit elements, lower interconnection lines, a second substrate, gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction and forming first and second stack structures, channel structures penetrating through the gate electrodes, and first and second contact plugs penetrating through the first and second stack structures, respectively, and connected to the gate electrodes. The first stack structure has first pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the first contact plugs, respectively. The second stack structure has second pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the second contact plugs, respectively. The first and second pad areas are offset in relation to each other so as not to overlap each other in the first direction.

公开(公告)号：US12075624B2

公开(公告)日：2024-08-27

申请号：US17378317

申请日：2021-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokcheon Baek ,  Younghwan Son ,  Miram Kwon ,  Junyong Park ,  Jiho Lee

IPC: H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: Provided is a three-dimensional semiconductor memory device including a first substrate that includes a cell array region and a connection region; first and second electrode layers that are sequentially stacked and spaced apart from each other on the first substrate, and an end portion of the first electrode layer and an end portion of the second electrode layer are offset from each other on the connection region; a first cell contact penetrating the second electrode layer and the first electrode layer such as to be connected to the second electrode layer on the connection region; and a first contact dielectric pattern between the first cell contact and the first electrode layer. The first cell contact includes columnar part that vertically extends from a top surface of the first substrate, and a connection part that laterally protrudes from the columnar part and contacts the second electrode layer.