公开(公告)号：US20250014986A1

公开(公告)日：2025-01-09

申请号：US18748662

申请日：2024-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Rui ZHANG ,  Kyoungsoo Kim ,  WooPoung Kim

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package comprises a core layer, an integrated stack capacitor (ISC) on the core layer, one or more build-up layers on the core layer in which the ISC is embedded, and one or more metal layers on the core layer.

公开(公告)号：US11495576B2

公开(公告)日：2022-11-08

申请号：US16822693

申请日：2020-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungsoo Kim ,  Sunwon Kang ,  Seungduk Baek ,  Ho Geon Song ,  Kyung Suk Oh

IPC: H01L23/498 ,  H01L23/48 ,  H01L23/544 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a first die including a signal region and a peripheral region bordering the signal region and having first vias in the peripheral region, a second die stacked on the first die and having second vias at positions corresponding to the first vias in the peripheral region, and first connection terminals between the first die and the second die that are configured to connect the second vias to the first vias, respectively. The peripheral region includes first regions and second regions configured to transmit different signals, which are alternately arranged in a first direction. The first vias are arranged in at least two rows along a second direction intersecting the first direction in each of the first and second regions.

公开(公告)号：US10720408B2

公开(公告)日：2020-07-21

申请号：US16684569

申请日：2019-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungsoo Kim ,  SunWon Kang

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/498 ,  H01L23/50 ,  H01L25/10

Abstract: A semiconductor module, comprising: a module substrate with an electric connection element; at least one semiconductor package provided on the module substrate, the at least one semiconductor package including a plurality of semiconductor chips; and a connection region electrically connecting the semiconductor package to the module substrate, wherein the connection region comprises: a first region electrically connected between data signal terminals of a first chip of the semiconductor chips of the semiconductor package and the module substrate; a second region electrically connected between data signal terminals of a second chip of the semiconductor chips of the semiconductor package and the module substrate; and a third region electrically connected between command/address signal terminals of both the first and second chips of the semiconductor package and the module substrate, wherein the first region is closer to the electric connection element of the module substrate, compared with the third region.

公开(公告)号：US20210005576A1

公开(公告)日：2021-01-07

申请号：US16822693

申请日：2020-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungsoo Kim ,  Sunwon Kang ,  Seungduk Baek ,  Ho Geon Song ,  Kyung Suk Oh

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a first die including a signal region and a peripheral region bordering the signal region and having first vias in the peripheral region, a second die stacked on the first die and having second vias at positions corresponding to the first vias in the peripheral region, and first connection terminals between the first die and the second die that are configured to connect the second vias to the first vias, respectively. The peripheral region includes first regions and second regions configured to transmit different signals, which are alternately arranged in a first direction. The first vias are arranged in at least two rows along a second direction intersecting the first direction in each of the first and second regions.