Apparatus, memory device, and method for storing multiple parameter codes for operation parameters

    公开(公告)号:US11545196B2

    公开(公告)日:2023-01-03

    申请号:US17466754

    申请日:2021-09-03

    IPC分类号: G11C7/10 G11C7/14

    摘要: Provided are an apparatus, a memory device, and a method for storing a plurality of parameter codes for an operation parameter. The memory device includes a mode register and a control logic circuit. To set a first operating condition and a second operating condition for one operation parameter, the mode register stores a first parameter code for the operation parameter and a second parameter code, which is expressed as an offset value from the first parameter code. The control logic circuit sets the first operating condition as a current operating condition of the memory device by using the first parameter code based on a first control code and sets the second operating condition as the current operating condition of the memory device by using the first parameter code and the second parameter code based on a second control code.

    MEMORY DEVICE PERFORMING OFFSET CALIBRATION AND OPERATING METHOD THEREOF

    公开(公告)号:US20230129949A1

    公开(公告)日:2023-04-27

    申请号:US17968052

    申请日:2022-10-18

    IPC分类号: G11C7/10

    摘要: Disclosed are a memory device that performs offset calibration and a method of operating the memory device. The memory device includes an input/output pad configured to receive data from a device external, an on-die termination (ODT) circuit connected to the input/output pad, a plurality of receivers connected to the ODT circuit and configured to receive the data from the input/output pad, an offset calibration circuit configured to perform an offset calibration operation on data output from the plurality of receivers and output an offset correction, a first switch configured to provide a first voltage to the plurality of receivers, and a second switch configured to provide a second voltage to the plurality of receivers. During the offset calibration operation, the plurality of receivers receive a third voltage in response to the ODT circuit being enabled and the first voltage through the first switch.

    Memory device performing offset calibration and operating method thereof

    公开(公告)号:US12125553B2

    公开(公告)日:2024-10-22

    申请号:US17968052

    申请日:2022-10-18

    IPC分类号: G11C7/10

    摘要: Disclosed are a memory device that performs offset calibration and a method of operating the memory device. The memory device includes an input/output pad configured to receive data from a device external, an on-die termination (ODT) circuit connected to the input/output pad, a plurality of receivers connected to the ODT circuit and configured to receive the data from the input/output pad, an offset calibration circuit configured to perform an offset calibration operation on data output from the plurality of receivers and output an offset correction, a first switch configured to provide a first voltage to the plurality of receivers, and a second switch configured to provide a second voltage to the plurality of receivers. During the offset calibration operation, the plurality of receivers receive a third voltage in response to the ODT circuit being enabled and the first voltage through the first switch.

    Apparatus, memory device, and method for storing multiple parameter codes for operation parameters

    公开(公告)号:US11688438B2

    公开(公告)日:2023-06-27

    申请号:US18071054

    申请日:2022-11-29

    IPC分类号: G11C7/10 G11C7/14

    摘要: Provided are an apparatus, a memory device, and a method for storing a plurality of parameter codes for an operation parameter. The memory device includes a mode register and a control logic circuit. To set a first operating condition and a second operating condition for one operation parameter, the mode register stores a first parameter code for the operation parameter and a second parameter code, which is expressed as an offset value from the first parameter code. The control logic circuit sets the first operating condition as a current operating condition of the memory device by using the first parameter code based on a first control code and sets the second operating condition as the current operating condition of the memory device by using the first parameter code and the second parameter code based on a second control code.