公开(公告)号：US20240147706A1

公开(公告)日：2024-05-02

申请号：US18370149

申请日：2023-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keunui KIM ,  Kiseok LEE ,  Eunsuk JANG ,  Seokhan PARK ,  Seok-Ho SHIN ,  Joongchan SHIN ,  Moonyoung JEONG

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/315 ,  H10B12/482 ,  H10B12/50

Abstract: A semiconductor memory device may include a substrate, a bit line extending in a first direction on the substrate, a first word line and a second word line extending in a second direction to cross the bit line, a back-gate electrode extending in the second direction between the first word line and the second word line, first and second active patterns disposed between the first and second word lines and the back-gate electrode and connected to the bit line, contact patterns coupled to the first and second active patterns, respectively, a first back-gate capping pattern between the contact patterns and the back-gate electrode, and first gate capping patterns between the contact patterns and the first and second word lines. The first back-gate capping pattern and the first gate capping pattern may have first and second seams, which are extended in the second direction and are located at different vertical levels.

公开(公告)号：US20250107071A1

公开(公告)日：2025-03-27

申请号：US18671624

申请日：2024-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taegyu KANG ,  Keunui KIM ,  Seokhan PARK ,  Joongchan SHIN ,  Gyuhwan OH ,  Bowon YOO ,  Kiseok LEE ,  Sangho LEE ,  Eunsuk JANG ,  Moonyoung JEONG

IPC: H10B12/00

Abstract: A semiconductor device comprising: a substrate; bit lines on the substrate; word lines on the bit lines, wherein the word lines are spaced apart from each other in a first direction; activation patterns between the word lines; a back gate electrode between the activation patterns, wherein the back gate electrode extends in a second direction; and a first gate separation pattern between the word lines in the first direction, wherein a portion of the word lines is a space between the activation patterns in the second direction and the word lines extend around the activation patterns, wherein the word lines and the first gate separation pattern each include a first surface facing the bit lines and a second surface opposite to the first surface in a third direction, wherein the first gate separation pattern is closer than the word lines to the bit lines in the third direction.

公开(公告)号：US20250107075A1

公开(公告)日：2025-03-27

申请号：US18809859

申请日：2024-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan KIM ,  Joongchan SHIN ,  Hyungeun CHOI ,  Taegyu KANG ,  Keunui KIM ,  Bowon YOO

IPC: H10B12/00

Abstract: A semiconductor device includes a substrate including a cell array area and an interface area, bit lines on the cell array area and extending in a first horizontal direction, back gate lines on the bit lines and extending in a second direction, insulating blocks on the interface area and each overlapping the back gate lines in the second direction, word lines among which each pair of two adjacent word lines are on both sides of a corresponding back gate line, respectively, and extending on a sidewall of a corresponding insulating block, active semiconductor layers each between a corresponding back gate line and a corresponding word line on the cell array area and having one end electrically connected to a corresponding bit line, and a word line contact on the interface area and on a corresponding word line and a corresponding insulating block adjacent thereto.