公开(公告)号：US20240049441A1

公开(公告)日：2024-02-08

申请号：US18131917

申请日：2023-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juseong OH

IPC: H10B12/00

CPC classification number: H10B12/0335 ,  H10B12/50 ,  H10B12/482 ,  H10B12/315 ,  H01L28/75

Abstract: A semiconductor device includes a substrate; lower electrodes on the substrate; a dielectric layer on the lower electrodes; an upper electrode on the dielectric layer; a contact structure connected to the upper electrode; and a wiring layer on the contact structure, wherein the contact structure includes a lower plug, and an upper plug on the lower plug, an upper surface of the lower plug is substantially coplanar with an upper surface of the upper electrode, a first width of the upper surface of the lower plug is narrower than a second width of a lower surface of the upper plug, and the lower surface of the upper plug is in contact with the upper surface of the lower plug.

公开(公告)号：US20240008260A1

公开(公告)日：2024-01-04

申请号：US18368939

申请日：2023-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyoung CHOI ,  Juseong OH ,  Yoosang HWANG

IPC: H10B12/00 ,  H01L23/522 ,  H01L23/528 ,  G11C5/10

CPC classification number: H10B12/37 ,  H01L28/60 ,  H01L23/5226 ,  H01L23/528 ,  G11C5/10

Abstract: A semiconductor device includes a substrate including a cell area having a first active region and a peripheral circuit area having a second active region, a direct contact contacting the first active region in the cell area, a bit line structure disposed on the direct contact, a capacitor structure electrically connected to the first active region, a gate structure disposed on the second active region in the peripheral circuit area, lower wiring layers disposed adjacent to the gate structure and electrically connected to the second active region, upper wiring layers disposed on the lower wiring layers, a wiring insulating layer disposed between the lower wiring layers and the upper wiring layers, and upper contact plugs connected to at least one of the lower wiring layers and the upper wiring layers and extending through the wiring insulating layer.

公开(公告)号：US20220399343A1

公开(公告)日：2022-12-15

申请号：US17568440

申请日：2022-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyoung CHOI ,  Juseong OH ,  Yoosang HWANG

IPC: H01L27/108 ,  H01L49/02 ,  G11C5/10 ,  H01L23/528 ,  H01L23/522

Abstract: A semiconductor device includes a substrate including a cell area having a first active region and a peripheral circuit area having a second active region, a direct contact contacting the first active region in the cell area, a bit line structure disposed on the direct contact, a capacitor structure electrically connected to the first active region, a gate structure disposed on the second active region in the peripheral circuit area, lower wiring layers disposed adjacent to the gate structure and electrically connected to the second active region, upper wiring layers disposed on the lower wiring layers, a wiring insulating layer disposed between the lower wiring layers and the upper wiring layers, and upper contact plugs connected to at least one of the lower wiring layers and the upper wiring layers and extending through the wiring insulating layer.