知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.032 seconds)

    Semiconductor package
    2.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US12154889B2

    公开(公告)日：2024-11-26

    申请号：US17370594

    申请日：2021-07-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunsoo Chung ,  Taewon Yoo ,  Myungkee Chung ,  Jinchan Ahn

    IPC: H01L23/64 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10

    Abstract: Disclosed is a semiconductor package comprising a semiconductor chip and a redistribution layer. The semiconductor chip includes a semiconductor substrate, a passivation layer, and first power, second power, and signal pads exposed from the passivation layer. The redistribution layer includes a photosensitive dielectric layer, and first to third redistribution patterns and a high-k dielectric pattern that are in the photosensitive dielectric layer. The first, second, and third redistribution patterns are respectively connected to the first power, second power, and signal pads. The high-k dielectric pattern is between the first and second redistribution patterns. The photosensitive dielectric layer includes a first dielectric material. The high-k dielectric pattern includes a second dielectric material whose dielectric constant greater than that of the first dielectric material. The high-k dielectric pattern is in contact with the passivation layer. The passivation layer includes a dielectric material different from the first and second dielectric materials.

    SEMICONDUCTOR PACKAGE
    4.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250149519A1

    公开(公告)日：2025-05-08

    申请号：US18769823

    申请日：2024-07-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunsoo Chung ,  Jinchan Ahn ,  Chiwoo Lee

    IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H10B80/00

    Abstract: A semiconductor package includes a package substrate, a plurality of stacked structures on the package substrate, each stacked structure including a plurality of core chips stacked on each other, each core chip including a memory cell array including a plurality of memory cells, a buffer chip on the package substrate, and spaced apart from the plurality of stacked structures in a horizontal direction, and a photonics package including an optical integrated circuit chip on the package substrate, an electronic integrated circuit chip on the optical integrated circuit chip, and a first molding layer surrounding side surfaces of the electronic integrated circuit chip, wherein the buffer chip is configured to control the memory cell of the core chip of each of the plurality of stacked structures.

    Circuit boards and semiconductor packages including the same
    7.
    发明授权
    Circuit boards and semiconductor packages including the same 有权

    公开(公告)号：US10141255B2

    公开(公告)日：2018-11-27

    申请号：US15994004

    申请日：2018-05-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： MuSeob Shin ,  Won-young Kim ,  Sanghyun Park ,  Jinchan Ahn

    IPC: H01L23/498 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

    Abstract: A circuit board and a semiconductor packages therewith are disclosed. The circuit board may include a top surface, on which at least one semiconductor chip is mounted, and a bottom surface, to which at least one outer terminal is coupled. The top surface may include an upper window region, on which an upper conductive pattern electrically connected to the semiconductor chip is provided, and the bottom surface may include a lower window region, on which a lower conductive pattern electrically connected to the upper conductive pattern is provided. Here, a ratio of an area of the lower conductive pattern to an area of the upper conductive pattern may be less than or equal to 1.5.

    Semiconductor device having metal bump and method of manufacturing the same
    10.
    发明授权
    Semiconductor device having metal bump and method of manufacturing the same 有权

    公开(公告)号：US11037894B2

    公开(公告)日：2021-06-15

    申请号：US16923406

    申请日：2020-07-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinchan Ahn ,  Won-young Kim ,  Chanho Lee

    IPC: H01L23/00 ,  H01L23/522

    Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a metal line layer on a semiconductor substrate, and a metal terminal on the metal line layer. The metal line layer includes metal lines, and a passivation layer having a non-planarized top surface including flat surfaces on the metal lines and a concave surface between the metal lines. The metal terminal is provided on the passivation layer. Opposite lateral surfaces of the metal terminal facing each other are provided on the flat surfaces of the passivation layer.

Patent Agency Ranking