公开(公告)号：US20200065453A1

公开(公告)日：2020-02-27

申请号：US16670282

申请日：2019-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-won KIM ,  Jae-pil Shin ,  Tae-heon Kim ,  Yong-hyeon Kim ,  Tae-hyun Kim ,  Jin-kyu Park

IPC: G06F17/50

Abstract: Patterns in an integrated circuit may be evaluated, and a semiconductor device may be fabricated based on the evaluation. The evaluation may include a extracting and superimposing first patterns corresponding to design patterns of the same shape from input layout data generated based on inspecting the integrated circuit, generating distribution data of the first patterns based on the superimposed first patterns, determining an evaluation contour of the design patterns based on an evaluation condition and the distribution data, and generating output layout data based on replacing the first patterns with second patterns each having the evaluation contour. Weak points in the integrated circuit may be detected based on the output layout data. The fabricating may include selectively incorporating an integrated circuit into a semiconductor device based on a determination that the integrated circuit includes less than a threshold quantity and/or threshold concentration of weak points.

公开(公告)号：US10885261B2

公开(公告)日：2021-01-05

申请号：US16670282

申请日：2019-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-won Kim ,  Jae-pil Shin ,  Tae-heon Kim ,  Yong-hyeon Kim ,  Tae-hyun Kim ,  Jin-kyu Park

IPC: G06F30/00 ,  G06F30/398

Abstract: Patterns in an integrated circuit may be evaluated, and a semiconductor device may be fabricated based on the evaluation. The evaluation may include a extracting and superimposing first patterns corresponding to design patterns of the same shape from input layout data generated based on inspecting the integrated circuit, generating distribution data of the first patterns based on the superimposed first patterns, determining an evaluation contour of the design patterns based on an evaluation condition and the distribution data, and generating output layout data based on replacing the first patterns with second patterns each having the evaluation contour. Weak points in the integrated circuit may be detected based on the output layout data. The fabricating may include selectively incorporating an integrated circuit into a semiconductor device based on a determination that the integrated circuit includes less than a threshold quantity and/or threshold concentration of weak points.

公开(公告)号：US10509885B2

公开(公告)日：2019-12-17

申请号：US15716856

申请日：2017-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-won Kim ,  Jae-pil Shin ,  Tae-heon Kim ,  Yong-hyeon Kim ,  Tae-hyun Kim ,  Jin-kyu Park

IPC: G06F17/50

Abstract: Patterns in an integrated circuit may be evaluated, and a semiconductor device may be fabricated based on the evaluation. The evaluation may include a extracting and superimposing first patterns corresponding to design patterns of the same shape from input layout data generated based on inspecting the integrated circuit, generating distribution data of the first patterns based on the superimposed first patterns, determining an evaluation contour of the design patterns based on an evaluation condition and the distribution data, and generating output layout data based on replacing the first patterns with second patterns each having the evaluation contour. Weak points in the integrated circuit may be detected based on the output layout data. The fabricating may include selectively incorporating an integrated circuit into a semiconductor device based on a determination that the integrated circuit includes less than a threshold quantity and/or threshold concentration of weak points.

公开(公告)号：US09122216B2

公开(公告)日：2015-09-01

申请号：US14028865

申请日：2013-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-kyu Park ,  Jin-hwi Jun ,  Jung-ho Bang

IPC: G03G15/00 ,  H04N1/00 ,  G06F3/12

CPC classification number: G03G15/5004 ,  G03G15/5075 ,  G03G2215/00109 ,  G06F3/1213 ,  G06F3/1221 ,  G06F3/1229 ,  G06F3/1261 ,  G06F3/1285 ,  G06F3/1288 ,  G06F3/1291 ,  H04N1/00896 ,  H04N1/00954 ,  H04N2201/0082 ,  H04N2201/0094 ,  Y02D10/1592

Abstract: An image forming apparatus includes a storage unit, an interface unit which is connected to a host apparatus and at least one of other image forming apparatuses, an image forming unit which prints image data received through the interface unit, and a controller which, if image data is received when the image forming apparatus is in a normal mode, controls the image forming unit to perform an image forming job using the image data, and if the image data is received when the image forming apparatus is in a power saving mode, controls the interface unit to transmit the image data to another image forming apparatus so that the another image forming apparatus performs an image forming job.

Abstract translation: 图像形成装置包括：存储单元，连接到主机装置的接口单元和其他图像形成装置中的至少一个;打印通过接口单元接收的图像数据的图像形成单元;以及控制器，如果图像 当图像形成装置处于正常模式时接收数据，控制图像形成单元使用图像数据执行图像形成作业，并且如果在图像形成装置处于省电模式时接收到图像数据，则控制 所述接口单元将图像数据发送到另一图像形成装置，使得另一图像形成装置执行图像形成作业。