公开(公告)号：US20250015018A1

公开(公告)日：2025-01-09

申请号：US18626727

申请日：2024-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin YANG

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: Provided is a semiconductor package which includes: a redistribution layer including at least one insulation layer in which a plurality of wiring patterns are formed; a semiconductor chip, on the redistribution layer, connected to at least one of the plurality of wiring patterns; and a capacitor disposed in the redistribution layer.

公开(公告)号：US20250167193A1

公开(公告)日：2025-05-22

申请号：US18807904

申请日：2024-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin YANG ,  WooPoung KIM

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H10B12/00 ,  H10B80/00

Abstract: A method, system, and device are disclosed herein where a first layer includes at least one transistor, a second layer on a first side of the first layer includes a signal network, a third layer on a second side of the first layer, opposite the first side, includes a backside power delivery network, and a memory module is coupled to the signal network. The backside power delivery network, the at least one transistor, and the signal network may provide a logic circuit for the memory module.

公开(公告)号：US20250112157A1

公开(公告)日：2025-04-03

申请号：US18655217

申请日：2024-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin YANG ,  WooPoung KIM

IPC: H01L23/532 ,  H01L21/768

Abstract: A method, system, and devices are disclosed herein involving a first substrate with a first grain layer, a second substrate with a second grain layer, and a third grain layer contacting the first grain layer and the second grain layer. The third grain layer having an average grain size smaller than the first grain layer and second grain layer.

公开(公告)号：US20250118720A1

公开(公告)日：2025-04-10

申请号：US18823660

申请日：2024-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin YANG ,  WooPoung KIM ,  Ramkumar SUBRAMANIAN ,  Sriram BALASUBRAMANIAN ,  Martin SCOTT

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H10B80/00

Abstract: Disclosed herein are methods, systems and devices including a first layer, the first layer including a first compute device, a first multi-device package, and a second multi-device package. The first compute device may be between the first multi-device package and the second multi-device package. A second layer may include a first redistribution layer on a first side of the second layer facing the first layer, the first redistribution layer electrically connecting the first compute device to the first multi-device package and the first redistribution layer electrically connecting the first compute device to the second multi-device package. The first layer may include a third multi-device package and a fourth multi-device package, with the first compute device between the third multi-device package and the fourth multi-device package.

公开(公告)号：US20250118677A1

公开(公告)日：2025-04-10

申请号：US18791420

申请日：2024-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin YANG ,  WooPoung KIM ,  Ramkumar SUBRAMANIAN ,  Sriram BALASUBRAMANIAN ,  Martin Philip SCOTT

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: A method, system and devices are disclosed providing a first layer, the first layer including a first device region and a second device region, and a second layer including an interconnection die, the interconnection die including an interface logic. The first device region and the second device region are mounted on a first side of the interconnection die, and the first device region and the second device region are communicatively coupled to the interface logic.

公开(公告)号：US20250014985A1

公开(公告)日：2025-01-09

申请号：US18625690

申请日：2024-04-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin YANG

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

Abstract: Provided is a semiconductor package which includes: a die stack including at least two semiconductor chips laterally arranged and isolated from each other by a molding material; and an interconnect package disposed above or below the die stack and connecting the semiconductor chips to each other, wherein the interconnect package having a smaller lateral width than the die stack is entirely overlapped by the die stack in a vertical direction, and a capacitor is disposed inside the interconnect package and connected to at least one of the semiconductor chips and configured to be connected to a voltage source and a ground.