公开(公告)号：US20180294225A1

公开(公告)日：2018-10-11

申请号：US15855416

申请日：2017-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： TaeHee Lee ,  Juyeon LEE ,  Jeehoon HWANG

IPC: H01L23/528 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11526 ,  H01L27/11573

Abstract: Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate a substrate including a peripheral circuit region and a cell array region, an electrode structure including a plurality of electrodes vertically stacked on the cell array region of the substrate, a peripheral logic circuit provided on the peripheral circuit region of the substrate, the peripheral logic circuit including a first impurity region doped with first impurities, a peripheral contact plug connected to the first impurity region, and a second impurity region between the first impurity region and the peripheral contact plug, the second impurity region being including second impurities different from the first impurities. The peripheral contact plug includes a lower portion contacting the second impurity region, and an upper portion continuously extending from the lower portion a lower width of each of the lower and upper portions is less than an upper width thereof, and the upper width of the lower portion is greater than the lower width of the upper portion.