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    Display screen or portion thereof with graphical user interface
    1.
    外观设计
    Display screen or portion thereof with graphical user interface 有权

    公开(公告)号：USD1015347S1

    公开(公告)日：2024-02-20

    申请号：US29828351

    申请日：2022-02-25

    Applicant: Samsung Electronics Co., Ltd.

    Designer： Jaewon Park ,  Soeyoun Yim

    Abstract: FIG. 1 is a front view of a first embodiment of a display screen or portion thereof with graphical user interface showing our new design;
    FIG. 2 is a front view of a second embodiment thereof;
    FIG. 3 is a front view of a third embodiment thereof;
    FIG. 4 is a front view of a fourth embodiment thereof; and,
    FIG. 5 is a front view of a fifth embodiment thereof.
    The outermost broken line in the figures depicts a display screen or portion thereof that forms no part of the claimed design.
    The remaining broken lines in the figures depict portions of the graphical user interface which form no part of the claimed design.
    The grayscale shown in the figures represents a contrast in appearance.

    MEMORY DEVICE AND TEST METHOD OF MEMORY DEVICE
    2.
    发明公开
    MEMORY DEVICE AND TEST METHOD OF MEMORY DEVICE 审中-公开

    公开(公告)号：US20230402123A1

    公开(公告)日：2023-12-14

    申请号：US18059124

    申请日：2022-11-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaewon Park ,  Sukhan Lee

    IPC: G11C29/46 ,  G11C29/12 ,  G11C29/36

    CPC classification number: G11C29/46 ,  G11C29/12005 ,  G11C29/36 ,  G11C2029/3602

    Abstract: Provided is a memory device including a cell array, a peripheral circuit configured to control a memory operation of the plurality of memory cells, a test logic circuit configured to operate in a test mode and configured to perform a test operation on the plurality of memory cells, a first regulator configured to regulate a first power supply voltage received through a first pad and provide the first power supply voltage to at least one of the cell array and the peripheral circuit, and a power manager between the first pad and an input terminal of the first regulator, and between the first pad and the test logic circuit and configured to provide a test power supply voltage to the test logic circuit. In the test mode, while a first target voltage level of the first regulator fluctuates, a second target voltage level of the power manager is maintained constant.

    MEMORY DEVICE, TEST METHOD OF THE MEMORY DEVICE, AND METHOD OF MANUFACTURING MEMORY DEVICE INCLUDING THE TEST METHOD
    5.
    发明申请
    MEMORY DEVICE, TEST METHOD OF THE MEMORY DEVICE, AND METHOD OF MANUFACTURING MEMORY DEVICE INCLUDING THE TEST METHOD 有权

    公开(公告)号：US20250104791A1

    公开(公告)日：2025-03-27

    申请号：US18668224

    申请日：2024-05-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaewon Park ,  Jaehoon Lee ,  Kyomin Sohn

    IPC: G11C29/18

    Abstract: A memory device includes: a built-in self-test circuit configured to select a first target bank and a second target bank for each of a plurality of row addresses such that each of a plurality of memory banks is selected as the first target bank and the second target bank at least once, and to perform parallel tests on the first and second target banks for each of the plurality of row addresses; a comparator configured to compare first data output from the first target bank and second data output from the second target bank, and to output a fail signal according to a comparison result thereof; and a built-in analysis circuit configured to update a fail bank table indicating fail information of each of the plurality of memory banks, in response to the fail signal, and to determine a defective bank by referring to the fail bank table.

    Memory device and test method of memory device
    8.
    发明授权
    Memory device and test method of memory device 有权

    公开(公告)号：US12266414B2

    公开(公告)日：2025-04-01

    申请号：US18059124

    申请日：2022-11-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaewon Park ,  Sukhan Lee

    IPC: G11C29/46 ,  G11C29/12 ,  G11C29/36

    Abstract: Provided is a memory device including a cell array, a peripheral circuit configured to control a memory operation of the plurality of memory cells, a test logic circuit configured to operate in a test mode and configured to perform a test operation on the plurality of memory cells, a first regulator configured to regulate a first power supply voltage received through a first pad and provide the first power supply voltage to at least one of the cell array and the peripheral circuit, and a power manager between the first pad and an input terminal of the first regulator, and between the first pad and the test logic circuit and configured to provide a test power supply voltage to the test logic circuit. In the test mode, while a first target voltage level of the first regulator fluctuates, a second target voltage level of the power manager is maintained constant.

    Method of testing memory device, memory built-in self test (MBIST) circuit, and memory device for reducing test time
    9.
    发明授权
    Method of testing memory device, memory built-in self test (MBIST) circuit, and memory device for reducing test time 有权

    公开(公告)号：US11899959B2

    公开(公告)日：2024-02-13

    申请号：US17337992

    申请日：2021-06-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaewon Park ,  Sangkil Park ,  Jaehoon Lee

    IPC: G06F3/06

    CPC classification number: G06F3/0653 ,  G06F3/0614 ,  G06F3/0679

    Abstract: A method of testing a memory device, a memory built-in self-test (MBIST) circuit, and a memory device for improving reliability and reducing a test time. The memory device includes a plurality of memory banks and the MBIST circuit. The MBIST circuit is configured to generate double data rate (DDR) test patterns and parallel bit test (PBT) test patterns to test the memory banks. When a defective cell is detected as a result of the PBT test or the DDR test, the MBIST circuit is configured to perform a repair operation for replacing the defective cell with a redundancy cell and perform a re-test to verify the repair operation. The MBIST circuit may be configured to perform the DDR test on one or more memory cells including the defective cell during the re-test.

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