公开(公告)号：US20220326284A1

公开(公告)日：2022-10-13

申请号：US17513549

申请日：2021-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIHONG KIM ,  MINSEOK KIM ,  KIHYUN CHOI ,  HEEYOUB KANG ,  JOOYOUNG KIM ,  KWANGKYU BANG

IPC: G01R19/165 ,  G11C5/14 ,  G06F13/16 ,  G06F13/42 ,  G06F3/06 ,  G06F1/28 ,  G01K13/00 ,  G06K9/00 ,  G08B5/38

Abstract: Disclosed is a storage device, which includes a first nonvolatile memory device that stores user data, a second nonvolatile memory device that stores status information for fault analysis, a voltage detect circuit that detects whether an input voltage received at the storage device through a connector exceeds a reference voltage and outputs an over-voltage detect signal when the input voltage exceeds the reference voltage, a status display device that displays a status of the input voltage in response to a blink enable signal, and a storage controller that stores or reads the user data in or from the first nonvolatile memory device, outputs the blink enable signal to the status display device in response to the over-voltage detect signal, and stores the status information in the second nonvolatile memory device.

公开(公告)号：US20240215248A1

公开(公告)日：2024-06-27

申请号：US18219755

申请日：2023-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUN-MOOK CHOI ,  CHAE LYOUNG KIM ,  JIHONG KIM

IPC: H10B43/35 ,  H10B43/27

CPC classification number: H10B43/35 ,  H10B43/27

Abstract: A semiconductor device includes gate layers and lower insulating layers that are alternately stacked on an upper surface of a substrate, a channel structure passing through the gate layers and the lower insulating layers and extending in a vertical direction, a string select gate layer disposed on the channel structure, a string select channel structure passing through the string select gate layer and extending in the vertical direction, and a contact pad disposed in a space between the channel structure and the string select channel structure and connecting the channel structure to the string select channel structure. A lower surface of the contact pad contacts the channel structure and an upper surface of the contact pad contacts the string select channel structure. A first width of the lower surface of the contact pad is greater than a second width of a central portion of the contact pad. A third width of the upper surface of the contact pad is greater than the second width of the central portion of the contact pad.

公开(公告)号：US20240107775A1

公开(公告)日：2024-03-28

申请号：US18368098

申请日：2023-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunmook Choi ,  Hyunmog Park ,  JIHONG KIM

IPC: H10B51/20 ,  H10B51/30

CPC classification number: H10B51/20 ,  H10B51/30

Abstract: An integrated circuit device includes a plurality of conductive lines on a semiconductor substrate, the plurality of conductive lines extending in a horizontal direction and overlapping each other in a vertical direction, a plurality of insulating layers alternating with the plurality of conductive lines in a vertical direction and extending in the horizontal direction, and a channel structure extending through the plurality of conductive lines and the plurality of insulating layers in the vertical direction. The channel structure includes a core insulating layer, a channel layer on a side wall and a bottom surface of the core insulating layer, an information storage layer on an outside wall of the channel layer, and a pad pattern covering a top surface of the core insulating layer. The pad pattern contacts a portion of the outside wall of the channel layer and a topmost surface of the information storage layer.

公开(公告)号：US20240015967A1

公开(公告)日：2024-01-11

申请号：US18308393

申请日：2023-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SIYEON CHO ,  HYUNMOOK CHOI ,  JIHONG KIM

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: In a method of manufacturing a semiconductor device, an insulation layer and a first gate electrode layer are alternately and repeatedly formed on a substrate in a first direction perpendicular to an upper surface of the substrate to form a mold layer. The first gate electrode layer includes silicon doped with impurities having a first conductivity type. An opening is formed through the mold layer to expose the upper surface of the substrate. Portions of the first gate electrode layers adjacent to the opening are removed to form gaps, respectively. Horizontal channels are formed in the gaps, respectively. Each of the horizontal channels includes silicon doped with impurities having a second conductivity type. A vertical gate structure extending in the first direction is formed in the opening. A memory channel structure is formed through the mold layer to contact the upper surface of the substrate.