公开(公告)号：US20240306375A1

公开(公告)日：2024-09-12

申请号：US18444390

申请日：2024-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suyoun Song ,  Yoongoo Kang ,  Kyungwook Park ,  Youmin Ban ,  Changwoo Seo ,  Hyunchul Shim

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02

Abstract: An integrated circuit device includes a substrate having a plurality of active regions, a bit line extending in a horizontal direction on the substrate, an insulating capping pattern formed on the bit line and extending along the bit line, a direct contact disposed in a direct contact hole formed on the substrate and connected between a first active region selected from among the plurality of active regions and the bit line, and a spacer structure contacting a sidewall of the direct contact and a sidewall of the bit line The spacer structure includes a first spacer layer extending in a vertical direction on the sidewall of the direct contact and the sidewall of the bit line, and a second spacer layer covering at least a portion of the first spacer layer and extending in the vertical direction.